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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xilin Liu Milin Zhang Richardson, A.G. Lucas, T.H. Van der Spiegel, J. |
| Copyright Year | 2015 |
| Description | Author affiliation: Dept. of Neurosurg., Univ. of Pennsylvania, Philadelphia, PA, USA (Richardson, A.G.; Lucas, T.H.) || Dept. of Electr. & Syst. Eng., Univ. of Pennsylvania, Philadelphia, PA, USA (Xilin Liu; Milin Zhang; Van der Spiegel, J.) |
| Abstract | This paper presents a bidirectional neural interface, consisting of 12-channel low-noise amplifiers, channel-level neural feature extraction and proportional-integral-derivative (PID) controller, voltage and current mode analog-to-digital converters (ADC), and 12-channel multi-mode stimulators. The neural amplifier features a wide-band from 0.5Hz to 10kHz with a noise floor of 3.02μVrms. The input stage has been designed for high stimulation voltage tolerance, and fast stimulation artifact recovery. The digitally assisted, analog parallel feature extraction processor features an ultra low power consumption while performing 1) neural signal energy extraction in programmable frequency band and time window, or 2) action potential detection using a current-mode time-amplitude window discriminator. A programmable PID controller has been implemented at the channel-level for closed-loop operation. A 640nW 8-bit current-mode ADC featuring a FoM of 10.7fJ/conv-step at a sampling rate of 250kSps has been designed for action potential digitization, and a voltage-mode SAR ADC with a ENOB of 9.1 and FoM of 34.2fJ/conv-step has been implemented for neural features and local field potential digitizations. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4mA and a compliance voltage up to +/-5V in arbitrary channel configuration. The chip has been fabricated in 0.18μm HV-CMOS technology, occupying a silicon area of 2.2 mm2. The whole chip dissipates 276μW on average. Bench testing, in-vitro and in-vivo experimental results are presented in this paper. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 1506242 |
| Page Count | 4 |
| File Format | |
| e-ISBN | 9781479972340 |
| DOI | 10.1109/BioCAS.2015.7348339 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-10-22 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Wireless communication Electric potential Capacitors Bandwidth Feature extraction Frequency measurement System-on-chip |
| Content Type | Text |
| Resource Type | Article |
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