NDLI: Compact Models for Signal Transient and Crosstalk Noise of Coupled RLC Interconnect Lines with Ramp Inputs

Please wait, while we are loading the content...

2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications

4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)

Table of contents

Message from the General Chairs

Message from the Technical Program Chairs

A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 µm CMOS Process

Compensation-Capacitor Free Pseudo Three-Stage Amplifier with Large Capacitive Loads

The Design and Optimization of a 25 kS/s 10 bit Micropower Current S/H Cell for Weak Current Bio-medical Applications

A Single-Stage SEPIC PFC Converter for Multiple Lighting LED Lamps

Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC

Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction

Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems

Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications

A Fast Algorithm for the Chirp Rate Estimation

Crack Detection on Asphalt Surface Image Using Enhanced Grid Cell Analysis

Interpolation Models for Image Super-resolution

Performance Analysis of a Vehicle Crash Control System using Image

A High Speed CMOS Transmitter and Rail-to-Rail Receiver

Design of a 12-Channel 120-Gbs Optical Receiver Array in 0.18-µm CMOS Technology

99-dB High-Performance Delta-Sigma Modulator for 20-kHz Bandwidth

Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20 MHz Signal Bandwidth, 53.6 dB Dynamic Range and 51.4 dB SNDR

An FPGA Implementation of the Searcher Algorithm

Analysis of CPU Utilisation and Stack Consumption of a Multimedia Embedded System

Research on System Usability of Digital Libraries in China

A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application

Low Phase Noise Bond Wire VCO for DVB-H

A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM

A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications

A Multiprocessor System for a Small Size Soccer Robot Control System

Low Cost Arbitration Method for Arbitrarily Scalable Multiprocessor Systems

An Efficient Design of Single Event Transients Tolerance for Logic Circuits

Adaptive Diagnostic Pattern Generation for Scan Chains

Built-In Self-Test for Embedded Voltage Regulator

Recent Trends in FPGA Architectures and Applications

Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler

Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture

Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC

xDSL Network Upgrade Employing FPGAs

Power Issues on Circuit Design for Cochlear Implants

Architecture of a Low Storage Digital Pixel Sensor Array with an On-Line Block-Based Compression

Effects of Insulator Thickness on the Sensing Properties of MISiC Schottky-Diode Hydrogen Sensor

High Speed Depth Estimation Using Tilted Focal Planes

Multi-Phase Charge Pump Generating Positive and Negative High Voltages for TFT-LCD Gate Driving

Dynamic Co-operative Intelligent Memory

An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching

Proposal for a Bidirectional Gate Using Pseudo Floating-Gate

Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS

Compact Models for Signal Transient and Crosstalk Noise of Coupled RLC Interconnect Lines with Ramp Inputs

Improving Diagnosis Resolution without Physical Information

Predictive Die-Level Reliability-Yield Modeling for Deep Sub-micron Devices

Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance

FPGA implementation of a Single Pass Connected Components Algorithm

A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering Applications

Workload-Based Dynamic Voltage Scaling with the QoS for Streaming Video

Speech Recognition of Isolated Malayalam Words Using Wavelet Features and Artificial Neural Network

FPGA Based Real Time Solution for Sensitivity Time Control

A Jittered-Sampling Correction Technique for ADCs

Robust JPEG2000 Image Transmission over IEEE 802.15.4

New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits

Experimental Characterisations of Coupled Transmission Lines

A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata

A Test Data Compression Method for System-on-a-Chip

A Hybrid of Clonal Selection Algorithm and Frequency Sampling Method for Designing a 2-D FIR Filter

A Generation Flow for Self-Reconfiguration Controllers Customization

Design of High-Speed Floating Point Multiplier

High Performance Elliptic Curve Cryptographic Processor Over GF(2^163)

A Visual Notation for Processor and Resource Scheduling

Design for Testability of Functional Cores in High Performance Node Architectures

Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction

AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis

Oscillation-Based Test in Data Converters: On-Line Monitoring

A Case Study on At-Speed Testing for a Gigahertz Microprocessor

A Charge Pump Circuit --- Cascading High-Voltage Clock Generator

Threshold Voltage Start-up Boost Converter for Sub-mA Applications

Design of a Low-Voltage CMOS Charge Pump

High-Input Impedance Voltage-Mode Universal Biquadratic Filter with One input and Five Outputs Using DDCCs

Temporal-Spatial Correlation Based Mode Decision Algorithm for H.264/AVC Encoder

A Software-to-Hardware Self-Mapping Technique to Enhance Program Throughput for Portable Multimedia Workloads

Improved Policies for Drowsy Caches in Embedded Processors

Improving Cost-Effectiveness Using a Micro-level Static Architecture for Stream Applications

A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks

Temperature Modulation for Tin-Oxide Gas Sensors

Eigenspectra Palmprint Recognition

VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher

DWT/PCA Face Recognition using Automatic Coefficient Selection

A Spiking Neural Network for Gas Discrimination Using a Tin Oxide Sensor Array

A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing

A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow

High-Speed Priority Queue Architecture for Multiple Out Links

Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures

Drift Invariant Gas Recognition Technique for On Chip Tin Oxide Gas Sensor Array

On Using Fingerprint-Sensors for PIN-Pad Entry

FPGA Implementation of a Predictive Vector Quantization Image Compression Algorithm for Image Sensor Applications

Integrating Dynamic Load Balancing Strategies into the Car-Network

A Design of the Frequency Synthesizer for UWB Application in 0.13 µm RF CMOS Process

Analog to Digital Converter Specification for UMTS/FDD Receiver Applications

A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems

Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis

Scalable Montgomery Multiplier for Finite Fields GF(p) and GF(2^m)

Static Crosstalk Noise Analysis with Transition Map

Implementation of the Embedded System for Visually-Impaired People

Model-Based Gaze Direction Estimation in Office Environment

Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA

Configurable Blocks for Multi-precision Multiplication

High Performance FPGA Implementation of the Mersenne Twister

Addressing Heterogeneous Bandwidth Requirements in Modified Fat-Tree Networks-on-Chips

The Fourier Spectrum Analysis of Optical Feedback Self-Mixing Signal under Weak and Moderate Feedback

Elimination of ? Non-linear Luminance Effects for Digital Video Projection Phase Measuring Profilometers

Integrated CMOS Analog Neural Network Ability to Linearize the Distorted Characteristic of HPA Embedded in Satellites

Compact Gray-Code Counter/Memory Circuits for Spiking Pixels

Calibration and Debugging of Multi-step Analog to Digital Converters

A Prevenient Voltage Stress Test Method for High Density Memory

A Scan-Based Delay Test Method for Reduction of Overtesting

An Integrated Validation Environment for Differential Power Analysis

Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks

Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models

Low Voltage Design against Power Analysis Attacks

Electrical Power Monitoring System Using Thermochron Sensor and 1-Wire Communication Protocol

Efficient VLSI Layout of Edge Product Networks

Towards a Petri Net Based Approach to Model and Synthesise Dynamic Reconfiguration for FPGAs

Arbitrary Waveform Generator Based on Direct Digital Frequency Synthesizer

Design of a Data Concentrator Card for the Readout of the Compact Muon Solenoid Electromagnetic Calorimeter

A Novel Approach to High-Level Property Checking Using Wu's Method

Test Set Stripping Limiting the Maximum Number of Specified Bits

An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling

CreaTe: A New Programme to Attract Engineers as Design Artists

High-Performance Pseudorandom Number Generator Using Two-Dimensional Cellular Automata

Design Automation of UHF RFID Tag Antenna Design Using a Genetic Algorithm Linked to MWS CST

Compact Models for Signal Transient and Crosstalk Noise of Coupled RLC Interconnect Lines with Ramp Inputs

Content Provider	IEEE Xplore Digital Library
Author	Taehoon Kim Dongchul Kim Jung-A Lee Yungseon Eo
Copyright Year	2008
Description	Author affiliation: Hanyang Univ., Ansan (Taehoon Kim; Dongchul Kim; Jung-A Lee; Yungseon Eo)
Abstract	Analytical compact form models for the signal transient and crosstalk noise of two-coupled RLC lines are developed. Capacitive and inductive coupling effects are investigated and formulated in terms with eigen modes (i.e., even mode and odd mode). The signal transients and crosstalk noise expressions of two coupled lines are derived by using a wave-form approximation technique for the modal signals. It is shown that the models have excellent agreement with SPICE simulation.
Starting Page	205
Ending Page	209
File Size	656512
Page Count	5
File Format	PDF
ISBN	9780769531106
DOI	10.1109/DELTA.2008.7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power system transients Crosstalk Integrated circuit interconnections RLC circuits Electronic equipment testing transmission lines Analytical models inductance effect crosstalk signal transient Coupling circuits Voltage Transient analysis Signal design
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in