NDLI: Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture

Content Provider	IEEE Xplore Digital Library
Author	Zong Wang Arslan, T. Erdogan, A.
Copyright Year	2008
Description	Author affiliation: Univ. of Edinburgh, Edinburgh (Zong Wang; Arslan, T.; Erdogan, A.)
Abstract	Security issues emerged in recent years as the fast development of wireless technology, especially for mobile devices where computing resources are sparse. This paper presents the implementation of RC4 as well as AES (Advanced Encryption Standard) cipher algorithm, which are widely used in IEEE 802.11 as well as IEEE 802.16 and other standards. The implementations target a novel reconfigurable instruction cell array (RICA) based architecture which has recently been developed, with the aim of achieving low power, high performance and programming flexibility. As our simulation result shows RC4 stream cipher throughput achieves as high as 60 Mbps with 128 bits key size and 1024 bits data buffer packet. The AES algorithm has also been implemented on RICA, achieving a throughput of 55.6 Mbps with typical 128 bits key and 128 bits block size after optimization. Compared to commercial hardware encryption architecture of the same wireless application domain, our architecture exhibits superiority in several aspects.
Starting Page	148
Ending Page	152
File Size	2358907
Page Count	5
File Format	PDF
ISBN	9780769531106
DOI	10.1109/DELTA.2008.100
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	RC4 Data security Electronic equipment testing Throughput Batteries Communication system security Engines AES Wireless communication RICA Computer architecture Hardware Cryptography Hardware Encryption
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Implementation of AES/Rijndael on a dynamically reconfigurable architecture

An efficient and reconfigurable architecture for RC5

Design of a reconfigurable AES encryption/decryption engine for mobile terminals

AES crypto chip utilizing high-speed parallel pipelined architecture

An Area-Throughput Efficient FPGA Implementation of the Block Cipher AES Algorithm

A Compact Piplined Hardware Implementation of the AES-128 Cipher

Analysis of energy consumption of RC4 and AES algorithms in wireless LANs

Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine

Case study: integrated design of RC5 encryption

Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture

Similar Documents

Implementation of AES/Rijndael on a dynamically reconfigurable architecture

An efficient and reconfigurable architecture for RC5

Design of a reconfigurable AES encryption/decryption engine for mobile terminals

AES crypto chip utilizing high-speed parallel pipelined architecture

An Area-Throughput Efficient FPGA Implementation of the Block Cipher AES Algorithm

A Compact Piplined Hardware Implementation of the AES-128 Cipher

Analysis of energy consumption of RC4 and AES algorithms in wireless LANs

Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine

Case study: integrated design of RC5 encryption

Implementation of Hardware Encryption Engine for Wireless Communication on a Reconfigurable Instruction Cell Architecture