NDLI: Efficient VLSI Layout of Edge Product Networks

Content Provider	IEEE Xplore Digital Library
Author	Bakhshi, S. Sarbazi-Azad, H.
Copyright Year	2008
Description	Author affiliation: IPM Sch. of Comput. Sci., Tehran (Bakhshi, S.; Sarbazi-Azad, H.)
Abstract	The interconnection network between the processor cores in multiprocessors on chip has a crucial impact on the performance. Efficient VLSI layout area of such networks can result in lower costs and better performance. Layouts with more compact area can lead in shorter wires and therefore the signal propagation through the wires may take place in shorter time. In this paper, we study the VLSI layout bounds of a new product network, called the edge graph product. Lower bounds are usually computed by the crossing number and bisection width of the topological graphs. For computing the bisection width and crossing number of the edge graph product, we use the obtained upper bound on maximal congestion. We also represent efficient upper bounds on the layout area and maximum wire length by constructing layouts based on separators and bifurcators.
Starting Page	555
Ending Page	560
File Size	475111
Page Count	6
File Format	PDF
ISBN	9780769531106
DOI	10.1109/DELTA.2008.59
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Particle separators Electronic equipment testing Very large scale integration Bifurcation Networks on chip Application software Upper bound Network-on-a-chip Wires VLSI layout Labeling Collinear layout Edge graph product Interconnection networks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in