NDLI: Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20 MHz Signal Bandwidth, 53.6 dB Dynamic Range and 51.4 dB SNDR

Content Provider	IEEE Xplore Digital Library
Author	Tao Wang Liping Liang
Copyright Year	2008
Description	Author affiliation: Tsinghua Univ., Beijing (Tao Wang)
Abstract	This paper presents the non-idealities analysis, modelling and circuit implementation of a second-order two-bit Continuous-Time (CT) Sigma-Delta Modulator (SDM). The non-idealities such as quantizer metastability, clock jitter, finite integrator DC gain, circuit noises and non-linearities are discussed. Discrete time (DT) SDM model is first developed and then mapped onto CT-SDM model. Finally the circuit is implemented in 130 nm CMOS technology. It achieves a simulated 53.6 dB DR and 51.4 dB SNDR over a 20MHz signal bandwidth. The sampling clock frequency is 640 MHz, producing an Over-Sampling-Ratio (OSR) of 16. Second order loop is intrinsically stable, while higher order loops tend to be unstable and much effort must be taken to maintain stability. Multi-bit internal quantizer is employed to obtain more aggressive quantization noise suppression and lower clock jitter sensitivity compared with higher order single bit structure. Spectre simulation shows that the power dissipation of the circuit is about 6 mW at 1.8 V supply.
Starting Page	79
Ending Page	84
File Size	1121205
Page Count	6
File Format	PDF
ISBN	9780769531106
DOI	10.1109/DELTA.2008.17
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	ADC wide band Dynamic range Jitter Delta-sigma modulation Semiconductor device modeling sigma delta Bandwidth CMOS technology Circuit noise continuous time Signal analysis Signal design Clocks
Content Type	Text
Resource Type	Article

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