NDLI: HMIC wafer level packaging

Content Provider	IEEE Xplore Digital Library
Author	Boles, T. Hoag, D. Barter, M. Giacchino, R. Hogan, P. Goodrich, J.
Copyright Year	2009
Description	Author affiliation: M/A-COM Technology Solutions, Lowell, Massachusetts, 01851, USA (Boles, T.; Hoag, D.; Barter, M.; Giacchino, R.; Hogan, P.; Goodrich, J.)
Abstract	HMIC, an acronym for Heterolithic Microwave Integrated Circuits, is fundamentally a wafer level substrate which combines low, RF loss tangent glass with micromachined silicon to produce three dimensional circuitry with the capability to make RF, DC, and thermal vias as the device input and output. Using this technology both active and passive RF devices have been produced which have demonstrated excellent high frequency performance over a very broad range of frequencies from 1 MHz to as high as 110 GHz. This paper describes the development of a unique microwave and mmW packaging technique based upon the broadband high frequency properties of the basic HMIC technology. More specifically the results of utilizing the high frequency, 3-dimensional integration properties to provide a packaging medium that will enable active components, whether in flip chip or bondable configurations and including silicon, GaAs, or InP mixed materials, to be combined to create a surface mount wafer level multichip module is presented. It will be shown that this basic HMIC technology can also be applied to enable the incorporation of a hermetic solder seal silicon lid.
Starting Page	423
Ending Page	426
File Size	414442
Page Count	4
File Format	PDF
ISBN	9781424447497
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-09-28
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	EuMA
Subject Keyword	Radio frequency Integrated circuit technology Microwave integrated circuits Microwave devices Glass Packaging Microwave theory and techniques Silicon Radiofrequency integrated circuits Wafer scale integration
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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