NDLI: Experimental characterization and model validation of thermal hot spots in 3D stacked ICs

Content Provider	IEEE Xplore Digital Library
Author	Oprins, H. Cherman, V. Srinivasan, A. Cupak, M. Van der Plas, G. Marchal, P. Vandevelde, B. Cheng, E.
Copyright Year	2010
Description	Author affiliation: IMEC, Kapeldreef 75, B-3001 Leuven, Belgium (Oprins, H.; Cherman, V.; Cupak, M.; Van der Plas, G.; Marchal, P.; Vandevelde, B.) \|\| Gradient Design Automation Inc., 4633 Old Ironsides Drive, Santa Clara, CA 95054, USA (Srinivasan, A.; Cheng, E.)
Abstract	3D stacking of dies is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnections. The major bottleneck for 3D integration are thermal management issues due to the reduced thermal spreading in the thinned dies and the poor thermally conductive adhesives. In this paper, a dedicated thermal test vehicle with integrated heaters and sensors is presented to experimentally characterize the thermal behavior in 3D stacks. This test vehicle is used to validate a presented methodology for fine grain thermal analysis in 3D-ICs.
Starting Page	1
Ending Page	5
File Size	1481846
Page Count	5
File Format	PDF
ISBN	9781424484539
e-ISBN	9782355000126
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-06
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	EDA Publishing
Subject Keyword	Temperature measurement Temperature sensors Solid modeling software validation Heating thermal modeling Three dimensional displays Thermal analysis experimental characterization Through-silicon vias thermal aware design 3D stacked ICs
Content Type	Text
Resource Type	Article

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