NDLI: Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models

Content Provider	IEEE Xplore Digital Library
Author	Caldera, M. Calimera, A. Macii, A. Macii, E. Poncino, M.
Copyright Year	2010
Description	Author affiliation: Dipartimento di Automatica e Informatica DAUIN Politecnico di Torino, 10129, Torino (Caldera, M.; Calimera, A.; Macii, A.; Macii, E.; Poncino, M.)
Abstract	When considering modern ICs mapped onto nanometer CMOS technologies, increasingly higher power densities and larger power density spatial gradients are well known to be the main source of thermal hot-spots, which in turn may cause huge performance variations, low-energy efficiency, and thus, low reliability. The resulting difficulties in managing temperature have become one of the major challenges for circuit designers and EDA tools. In this work we present a gate-level thermal-aware low-power design technique, which aims at providing the circuit with temperature insensitivity (i.e., minimum timing variation under temperature fluctuations) while minimizing the active static power consumption. The proposed solution, based on a Simulated Annealing optimization algorithm applied on a ISING-like analytical model, exploits the Inverted Temperature Dependence (ITD) of nanometer CMOS gates. Under ITD, in fact, those gates that have low threshold voltages (LVT) show a delay which increases at higher temperature, while gates with high threshold voltage (HVT) show the opposite behavior, namely, they get faster as they get warmer. The right sequence of LVT and HVT cells may compensate the thermal effects on the critical paths, thus guaranteeing temperature insensitivity. Experimental results performed on a set of public benchmarks mapped onto an industrial 65nm technology show performance variations close to zero, with a significant leakage power reduction compared to standard single threshold voltage circuits.
Starting Page	1
Ending Page	6
File Size	271351
Page Count	6
File Format	PDF
ISBN	9781424484539
e-ISBN	9782355000126
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-06
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	EDA Publishing
Subject Keyword	Temperature measurement Temperature dependence Logic gates Threshold voltage Timing CMOS integrated circuits Integrated circuit modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Reconfigurable Threshold Logic Gates using memristive devices

Dual-threshold design of sub-threshold circuits

Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits

Effect of temperature dependence on performance of Digital CMOS circuit technologies

Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis

A modified CMOS nano-power resistorless current reference circuit

Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits

CMOS voltage reference with superior-order curvature-correction

A low-power dual threshold voltage-voltage scaling technique for domino logic circuits

Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models

Similar Documents

Reconfigurable Threshold Logic Gates using memristive devices

Dual-threshold design of sub-threshold circuits

Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits

Effect of temperature dependence on performance of Digital CMOS circuit technologies

Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis

A modified CMOS nano-power resistorless current reference circuit

Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits

CMOS voltage reference with superior-order curvature-correction

A low-power dual threshold voltage-voltage scaling technique for domino logic circuits

Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models