NDLI: Impact of PCB via and micro-via structures on component thermal performances

Content Provider	IEEE Xplore Digital Library
Author	Monier-Vinard, E. Bissuel, V. Daniel, O. Brizoux, M. Grivon, A. Pires, F. Maia, W.
Copyright Year	2010
Description	Author affiliation: THALES CORPORATE SERVICE, Meudon la foret France (Monier-Vinard, E.; Bissuel, V.; Daniel, O.; Brizoux, M.; Grivon, A.; Pires, F.; Maia, W.)
Abstract	Due to the packages getting smaller, their power dissipation is henceforth mainly drained through the PCB. Besides the dissipation challenges that are seen today with single-chip components will only be magnified with the extended introduction of multi-chip packaging such as the System in Package devices These high density packages have increased the cooling issues and are demanding more complex board designs to transfer the heat from their chips to the PCB ground planes. To remove the heat more efficiently from the package, via structures are now currently incorporated into the PCB sub layers, which act as the thermal path to the Printed Circuit Board inner traces and power layers. So, to optimize board cooling the designer has now to deal with PCB layer layout with conventional via structures and, in the near future, with the implementation of High Density Interconnection circuit boards and their sophisticated technology. In comparison to the conventional printed circuit technology, HDI will create still denser interconnect substrates, containing multi-level micro-via structures that play a decisive role in the miniaturization of circuit boards and will increase the cooling design complexity. Unfortunately, their Detailed Thermal Modelling remains a great challenge so the "Compact Thermal Model“ defined by the European DELPHI methodology with for end to minimize the size of the numerical models and to preserve a great accuracy for large set of boundary conditions has been investigated to propose a behavioural thermal resistance network dedicated to HDI board. That customized methodology was applied to local via and micro-via structures which have to be tied to emerging component packaging. The first results demonstrate that the coupled CTM of the board and the component offers a real opportunity to take into account more details of local board structure with a very good compliance, better than 95%, to DTM thermal behaviour. The capability, for modelling the thermal behaviour of this more complex devices is established in a work linked with EUREKA project IPITECH an acronym for Innovative PCB Integration Technologies for HDI board in Harsh environment.
Starting Page	1
Ending Page	6
File Size	675858
Page Count	6
File Format	PDF
ISBN	9781424484539
e-ISBN	9782355000126
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-06
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	EDA Publishing
Subject Keyword	Cooling Thermal resistance Heating Numerical models Copper Soldering
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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