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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hua-Hsin Yeh Shih-Hsu Huang Kuan-Hui Li |
| Copyright Year | 2011 |
| Description | Author affiliation: Department of Electronic Engineering, Chung Yuan Christian University, Chung Li, Taiwan, R.O.C. (Hua-Hsin Yeh; Shih-Hsu Huang; Kuan-Hui Li) |
| Abstract | Due to the low thermal conductivities of dielectrics between active layers, there is a strong demand to minimize the temperature rise of three-dimensional integrated circuits (3D ICs). In this paper, we demonstrate that, in the design of 3D ICs, different design partitioning results often lead to different amounts of temperature rise. However, to the best of our knowledge, no attention has been paid to the problem of design partitioning for temperature rise minimization. Based on that observation, we propose an integer linear programming (ILP) approach to find a design partitioning solution in which the amount of temperature rise is minimized. Compared with the previous work (that does not take the temperature rise into account), experimental results show that our approach can reduce 13.60% temperature rise without any extra overhead. |
| Starting Page | 447 |
| Ending Page | 450 |
| File Size | 559676 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781457713873 |
| ISSN | 21505934 |
| e-ISBN | 9781457713897 |
| e-ISBN | 9781457713880 |
| DOI | 10.1109/IMPACT.2011.6117253 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-10-19 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Integrated circuits Thermal resistance Benchmark testing Minimization Three dimensional displays Power dissipation |
| Content Type | Text |
| Resource Type | Article |
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