NDLI: The application of through silicon vias (or TSVs) for high power and temperature devices

Content Provider	IEEE Xplore Digital Library
Author	Ranade, A.P. Havens, R. Srihari, K.
Copyright Year	2014
Description	Author affiliation: Watson Inst. for Syst. Excellence, Binghamton Univ., Binghamton, NY, USA (Ranade, A.P.; Havens, R.; Srihari, K.)
Abstract	Miniaturization and higher functionality have been and continue to be serious pursuits of the electronics industry. In relation to the miniaturization of package size, the 3D integration of devices using through silicon vias (or TSVs) is currently being researched extensively. 2.5D integration with a passive interposer is currently being researched as a step toward achieving the goal of complete 3D integration. This paper analyzes the packaging industry's transition from 2D to 3D integration of packages. Literature focused on manufacturability, materials of interest, geometrical dimensions, market trends, and customer focus is discussed in detail. The utilization of TSV packages in high power and high temperature products is the research area still to be explored. Hence, existing simulation data is extrapolated to high power die dimensions to analyze the effect of package dimensions on the thermo-mechanical behavior of TSV power die. Furthermore, a basic thermo-mechanical model of a Cu-filled TSV passive interposer is studied under high power and high temperature field conditions. Multiple cases are simulated to study the effect of TSV dimensions and material properties on the thermo-mechanical behavior of power packages. The current limitations of TSVs in high power application s ar e stated based on the results.
Starting Page	1270
Ending Page	1278
File Size	937533
Page Count	9
File Format	PDF
ISBN	9781479952670
ISSN	10879870
DOI	10.1109/ITHERM.2014.6892427
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Through-silicon vias Three-dimensional displays Stress Packaging Silicon Thermomechanical processes Stacking high power and high temperature application TSV 2.5D and 3D integration thermo-mechanical analysis
Content Type	Text
Resource Type	Article

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2.5D/3D TSV processes development and assembly/packaging technology

TSVs in early layout design exploration for 3D ICs

Thermo-mechanical behavior of through silicon vias in a 3D integrated package with inter-chip microbumps

W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress

3D technology applications market trends & key challenges

Mechanical and thermo-mechanical stress considerations in applying 3D ICs to a design

Thermo-mechanical Stress of underfilled 3D IC packaging

Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration

3D integration of standard integrated circuits

The application of through silicon vias (or TSVs) for high power and temperature devices

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