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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Katoh, K. Tanabe, T. Zahidul, H.M. Namba, K. Ito, H. |
| Copyright Year | 2009 |
| Abstract | This paper proposes a delay measurement technique using signature registers, and a scan design for delay measurement utilizing the proposed delay measurement technique to detect small-delay defects. The delay of circuits can be measured with the scan design with lower area, smaller data volume, and shorter measurement time than with the conventional scan design for delay measurement. Accordingly, the small-delay defects outside the range of the normal-distributed delay are detected with lower cost. Evaluation with 0.18μm process shows that the area overhead of the proposed scan design is 32.2% smaller than that of the conventional method. The measurement time and the data volume for the measurement are reduced 66.7% and 66.0% compared with the conventional method, respectively. |
| Starting Page | 157 |
| Ending Page | 162 |
| File Size | 431837 |
| Page Count | 6 |
| File Format | |
| ISBN | 9780769538648 |
| ISSN | 10817735 |
| DOI | 10.1109/ATS.2009.54 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-11-23 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Measurement techniques Testing Clocks Time measurement Volume measurement Semiconductor device measurement Delay effects Area measurement Circuit faults Frequency small-delay defects signature register delay measurement scan design path delay fault |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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