NDLI: Customized Algorithms for High Performance Memory Test in Advanced Technology Node

Content Provider	IEEE Xplore Digital Library
Author	Shomo Chen Ning Huang Ting-Pu Tai Niu, A.
Copyright Year	2009
Abstract	Chip quality is becoming more difficult to maintain as the process geometry shrinks. Not only is design complexity higher, but new defect types cause DPM (defects per million) to increase. At the same time, the amount of embedded memory in many applications continues to grow, making memory testing a key factor in maintaining low cost and high quality in IC manufacturing. While commercial EDA tools are keeping pace with the need for greater test flow automation, new test algorithms are also needed to minimize the rate of field returns at advanced technology nodes. This paper describes how ASIC vendors can develop customized memory test algorithms to enhance their overall IC testing strategy.
Starting Page	87
Ending Page	89
File Size	332389
Page Count	3
File Format	PDF
ISBN	9780769538648
ISSN	10817735
DOI	10.1109/ATS.2009.41
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-23
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Decoding Fault detection Circuit testing Geometry Integrated circuit testing Built-in self-test Application specific integrated circuits Automatic testing Combinational circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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Customized Algorithms for High Performance Memory Test in Advanced Technology Node