NDLI: Fault Diagnosis Using Test Primitives in Random Access Memories

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Table of Contents

Steering Committee

Program Committee

Best Paper Award of ATS 2008

Call for Papers of ATS 2010

CA Based Built-In Self-Test Structure for SoC

A Random Jitter RMS Estimation Technique for BIST Applications

A Novel Seed Selection Algorithm for Test Time Reduction in BIST

Logic BIST Architecture for System-Level Test and Diagnosis

Fault Diagnosis under Transparent-Scan

Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns

On Improving Diagnostic Test Generation for Scan Chain Failures

On Scan Chain Diagnosis for Intermittent Faults

Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique

Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients

Low Cost Dynamic Test Methodology for High Precision ΣΔ ADCs

Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits

Scan Compression Implementation in Industrial Design - Case Study

Calibration as a Functional Test: An ADC Case Study

Customized Algorithms for High Performance Memory Test in Advanced Technology Node

A Practical DFT Approach for Complex Low Power Designs

DFT Challenges in Next Generation Multi-media IP

Yield Ramp up by Scan Chain Diagnosis

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing

New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology

Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing

Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder

A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems

Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug

A Post-Silicon Debug Support Using High-Level Design Description

A Low Overhead On-Chip Path Delay Measurement Circuit

An Adaptive Test for Parametric Faults Based on Statistical Timing Information

A Delay Measurement Technique Using Signature Registers

Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test

A Practical Approach to Threshold Test Generation for Error Tolerant Circuits

Speeding up SAT-Based ATPG Using Dynamic Clause Activation

N-distinguishing Tests for Enhanced Defect Diagnosis

Dynamic Compaction in SAT-Based ATPG

SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement

Transaction Level Modeling and Design Space Exploration for SOC Test Architectures

Efficient Software-Based Self-Test Methods for Embedded Digital Signal Processors

Is Low Power Testing Necessary? What does the Test Industry Truly Need?

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor

Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time

Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint

Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing

BIST Driven Power Conscious Post-Manufacture Tuning of Wireless Transceiver Systems Using Hardware-Iterated Gradient Search

Self-Calibrating Embedded RF Down-Conversion Mixers

A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis

Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATE

IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency

Multiple-Core under Test Architecture for HOY Wireless Testing Platform

Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies

Test Integration for SOC Supporting Very Low-Cost Testers

Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?

New Class of Tests for Open Faults with Considering Adjacent Lines

Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption

Deterministic Algorithms for ATPG under Leakage Constraints

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power

A Multi-dimensional Pattern Run-Length Method for Test Data Compression

Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage

Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?

A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities

Bridging Fault Diagnosis to Identify the Layer of Systematic Defects

Delay Fault Diagnosis in Sequential Circuits

A Partially-Exhaustive Gate Transition Fault Model

An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing

LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits

A Jitter Characterizing BIST with Pulse-Amplifying Technique

A Low-Cost Output Response Analyzer for the Built-in-Self-Test Σ-Δ Modulator Based on the Controlled Sine Wave Fitting Method

New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults

Testability Exploration of 3-D RAMs and CAMs

Fault Diagnosis Using Test Primitives in Random Access Memories

Test Generation for Designs with On-Chip Clock Generators

On the Generation of Functional Test Programs for the Cache Replacement Logic

Compact Test Generation for Small-Delay Defects Using Testable-Path Information

At-Speed Scan Test Method for the Timing Optimization and Calibration

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay

Analysis of Resistive Bridging Defects in a Synchronizer

On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification

Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks

2008 17th Asian Test Symposium

16th Asian Test Symposium (ATS 2007)

2006 15th Asian Test Symposium

14th Asian Test Symposium (ATS'05)

13th Asian Test Symposium

2003 Test Symposium

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

Proceedings 10th Asian Test Symposium

Proceedings of the Ninth Asian Test Symposium

Proceedings Eighth Asian Test Symposium (ATS'99)

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

Proceedings Sixth Asian Test Symposium (ATS'97)

Proceedings of the Fifth Asian Test Symposium (ATS'96)

Proceedings of the Fourth Asian Test Symposium

Proceedings of IEEE 3rd Asian Test Symposium (ATS)

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

Proceedings First Asian Test Symposium (ATS `92)

Fault Diagnosis Using Test Primitives in Random Access Memories

Content Provider	IEEE Xplore Digital Library
Author	Al-Ars, Z. Hamdioui, S.
Copyright Year	2009
Abstract	As diagnostic testing for memory devices increasingly gains in importance, companies are looking for flexible, cost effective methods to perform diagnostics on their failing devices. This paper proposes the new concept of test primitives as a method to diagnose memory faults. Test primitives provide an easy-to-use, extensible, low-cost memory fault diagnosis method that is universally applicable, since it uses simple platform-independent test sequences. The paper defines the concept of test primitives, shows their importance and gives examples to the way they are derived and used in a memory test environment.
Starting Page	403
Ending Page	408
File Size	309772
Page Count	6
File Format	PDF
ISBN	9780769538648
ISSN	10817735
DOI	10.1109/ATS.2009.79
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-23
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault diagnosis Random access memory Integrated circuit testing Costs System testing Fault detection Mathematics Performance gain Performance evaluation Manufacturing test optimization test primitives fault primitives memory testing fault diagnosis
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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