NDLI: An Adaptive Test for Parametric Faults Based on Statistical Timing Information

Content Provider	IEEE Xplore Digital Library
Author	Shintani, M. Uezono, T. Takahashi, T. Ueyama, H. Sato, T. Hatayama, K. Aikyo, T. Masu, K.
Copyright Year	2009
Abstract	The continuing miniaturization of LSI dimension is causing the increase of process-related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.
Starting Page	151
Ending Page	156
File Size	475020
Page Count	6
File Format	PDF
ISBN	9780769538648
ISSN	10817735
DOI	10.1109/ATS.2009.90
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-23
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Circuit faults Circuit testing Delay effects Propagation delay Semiconductor device testing Computer aided manufacturing Large scale integration Delay estimation Probability SSTA parametric fault path-delay test
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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