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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Katoh, K. Namba, K. Ito, H. |
| Copyright Year | 2010 |
| Description | Author affiliation: Department of Informatics & Imaging Systems, Chiba University, 1-33, Yayoi-cho, Inage-ku, Chiba-shi, 263-8522 Japan (Katoh, K.) || Graduate School of Advanced Integration Science, Chiba University, 1-33, Yayoi-cho, Inage-ku, Chiba-shi, 263-8522 Japan (Namba, K.; Ito, H.) |
| Abstract | This paper presents a low-area and short-time scan design for delay measurement using signature registers. The number of redundant latches is reduced utilizing X bits of test data for the delay measurement. After that, with the optimization of the scan chain routing, the scan chain length is reduced without decrease of the number of the measurable paths. These techniques keep the area overhead in the same order of that of the conventional scan designs for testing. In addition, the techniques further reduce the measurement time. Evaluation shows that the area overhead is 22.1% larger and 24.0% smaller than standard scan design and enhanced scan design respectively, which is in the order of scan designs for test. The measurement time is 90% shorter than that of standard scan design. |
| Starting Page | 311 |
| Ending Page | 314 |
| File Size | 238925 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424452699 |
| DOI | 10.1109/VDAT.2010.5496751 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-04-26 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Time measurement Testing Measurement techniques Area measurement Clocks Delay effects Length measurement Routing Latches Circuits |
| Content Type | Text |
| Resource Type | Article |
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