NDLI: Leveraging existing power control circuits and power delivery architecture for variability measurement

Content Provider	IEEE Xplore Digital Library
Author	Acharyya, D. Agarwal, K. Plusquellic, J.
Copyright Year	2010
Description	Author affiliation: Dept. of Electrical and Computer Engineering, Univ. of New Mexico, USA (Plusquellic, J.) \|\| Verigy Ltd., USA (Acharyya, D.) \|\| IBM Corp., USA (Agarwal, K.)
Abstract	Embedded test structures are increasingly being used to measure and analyze performance and power variations in product chips to better understand the impact of process variations. In this work, we propose a minimally-invasive, low-overhead technique for characterizing within-die and die-to-die leakage variation. The proposed technique leverages existing power control circuitry added by designers to reduce the power consumption of inactive functional units. We manipulate these ‘sleep islands’ to isolate and measure their leakage current contribution to the chip-wide leakage current. The measured set of sleep island leakage currents reflect the leakage current variation across the chip at a coarse level of resolution. In order to improve resolution, we propose a multiple power supply port (MSP) measurement technique to provide ‘within-island’ leakage current measurements. A calibration technique is described that corrects for differences between the sleep island and MSP approaches, effectively enabling the same information to be obtained using either technique. We demonstrate the techniques on a set of test chips fabricated in 65-nm SOI technology. The results show that leakage current variations across a small test structure array have both a locally random and globally deterministic component that can be accurately mapped using the sleep island or MSP approaches.
Starting Page	1
Ending Page	9
File Size	1922043
Page Count	9
File Format	PDF
ISBN	9781424472062
ISSN	10893539
e-ISBN	9781424472079
DOI	10.1109/TEST.2010.5699268
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Leakage current Sleep Current measurement Semiconductor device measurement Arrays Power measurement Calibration
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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