NDLI: Mask versus Schematic - an enhanced design-verification flow for first silicon success

Content Provider	IEEE Xplore Digital Library
Author	Tseng-Chin Luo Leong, E. Chao, M.C. Fisher, P.A. Chang, W.
Copyright Year	2010
Description	Author affiliation: Taiwan Semiconductor Manufacturing Corp., Hsinchu, Taiwan (Tseng-Chin Luo; Fisher, P.A.) \|\| Altera Corporation, USA (Leong, E.) \|\| Department of Electronics Engineering & Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan (Chao, M.C.; Chang, W.)
Abstract	Layout versus Schematic (LVS) is a commonly used technique employed at the design stage to insure the correctness of physical layout. However, as process technologies continually advance, increasingly complex boolean operations are required to produce the desired on-mask patterns, which are frequently optimized to enhance transistor performance and process margin. Design layout which has been verified by LVS may undergo substantial layout changes when subjected to the mask generation booleans, with potential implications for performance and margin estimation, particularly given the aggressive use of stressors in modern CMOS technologies. Errors in mask generation booleans, which are very difficult to detect by present primitive inspection methods, can easily result in functional failure although the initial LVS predicted success. Therefore, LVS performed at the design stage is no longer an iron-clad guarantee of chip functionality in advanced process technologies. In this paper, we introduce Mask-versus-Schematic (MVS) verification, a novel design verification flow which directly compares the schematic netlist with a netlist extracted after application of all mask generation booleans, in order to insure the correctness of the final mask data just before tapeout. Furthermore, the introduced methodology can be performed using currently available physical verification EDA tools. The experimental results presented here, using examples from some of the industry's most advanced process technology nodes, demonstrate the effectiveness and efficiency of this methodology in detecting errors resulting from mask generation boolean operations.
Starting Page	1
Ending Page	9
File Size	1037730
Page Count	9
File Format	PDF
ISBN	9781424472062
ISSN	10893539
e-ISBN	9781424472079
DOI	10.1109/TEST.2010.5699238
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Layout Logic gates Design automation Performance evaluation Foundries Integrated circuits Algorithm design and analysis
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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