NDLI: Automatic classification of bridge defects

Content Provider	IEEE Xplore Digital Library
Author	Nelson, J.E. Wing Chiu Tam Blanton, R.D.
Copyright Year	2010
Description	Author affiliation: Center for Silicon System Implementation, Carnegie Mellon University, Pittsburgh, PA 15213, USA (Nelson, J.E.; Wing Chiu Tam; Blanton, R.D.)
Abstract	A technique is proposed to automatically predict whether a failing chip has a bridge defect. Logic diagnosis is performed using scan test results to identify candidate nets. Several relevant features of the test data are measured for net pairs that consist of the diagnosis candidates and other nets in close physical proximity. Based on these features, rules are constructed to identify defects that fully exhibit classic bridge behaviors, while the remaining chips are classified using a forest of decision trees. Results indicate that a population of chips failing due to bridges can indeed be extracted with very high accuracy. Finally, the method correctly classifies 41 commercially-fabricated chips that underwent PFA.
Starting Page	1
Ending Page	10
File Size	698585
Page Count	10
File Format	PDF
ISBN	9781424472062
ISSN	10893539
e-ISBN	9781424472079
DOI	10.1109/TEST.2010.5699231
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bridges Logic gates Bridge circuits Barium Semiconductor device measurement Circuit faults Layout
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

"RESISTIVE SHORTS" WITHIN CMOS GATES

On modeling faults in FinFET logic circuits

Switch-level delay test of domino logic circuits

Deception by design: fooling ourselves with gate-level models

Diagnosis of Multiple Physical Defects Using Logic Fault Models

Testing CMOS logic gates for: realistic shorts

Test Generation for Weak Resistive Bridges

Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation

A comparison of bridging fault simulation methods

Automatic classification of bridge defects

Similar Documents

"RESISTIVE SHORTS" WITHIN CMOS GATES

On modeling faults in FinFET logic circuits

Switch-level delay test of domino logic circuits

Deception by design: fooling ourselves with gate-level models

Diagnosis of Multiple Physical Defects Using Logic Fault Models

Testing CMOS logic gates for: realistic shorts

Test Generation for Weak Resistive Bridges

Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation

A comparison of bridging fault simulation methods

Automatic classification of bridge defects