NDLI: Automated trace signals selection using the RTL descriptions

Content Provider	IEEE Xplore Digital Library
Author	Ho Fai Ko Nicolici, N.
Copyright Year	2010
Description	Author affiliation: Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada (Ho Fai Ko; Nicolici, N.)
Abstract	Pre-silicon verification has been traditionally used for eliminating design bugs before tape-out. However, due to the increasing design complexity and the limited accuracy in circuit modelling, the number of the design errors that escape to silicon continues to grow. This is aggravated by the interactions between multiple clock and power domains in the modern system-on-a-chip devices. As a result, structured methods for post-silicon debugging, which aim to detect and localize the bug escapes in silicon, have gained increasing attention in recent years. However, the existing approaches to aid post-silicon debugging primarily rely on the analysis performed using gate-level circuit descriptions. Since design entry is commonly done at the register transfer-level (RTL), the RTL information can be leveraged for the design of the on-chip debug hardware. In particular, in this paper we investigate how to automatically decide which signals to trace in real-time using the RTL information.
Starting Page	1
Ending Page	10
File Size	1088550
Page Count	10
File Format	PDF
ISBN	9781424472062
ISSN	10893539
e-ISBN	9781424472079
DOI	10.1109/TEST.2010.5699214
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Silicon Algorithm design and analysis Observability Debugging Computer bugs Real time systems
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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