NDLI: Tolerance of performance degrading faults for effective yield improvement

Content Provider	IEEE Xplore Digital Library
Author	Tong-Yu Hsieh Breuer, M.A. Annavaram, M. Gupta, S.K. Kuen-Jong Lee
Copyright Year	2009
Description	Author affiliation: Dept. of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan (Tong-Yu Hsieh; Kuen-Jong Lee) \|\| Dept. of Electrical Engineering, University of Southern California, Los Angeles, USA (Breuer, M.A.; Annavaram, M.; Gupta, S.K.)
Abstract	To provide a new avenue for improving yield for nano-scale fabrication processes, we introduce a new notion: performance degrading faults (pdef). A fault is said to be a pdef if it cannot cause a functional error at system outputs but may result in system performance degradation. In a processor, a fault is a pdef if it causes no error in the execution of user programs but may reduce performance, e.g., decrease the number of instructions executed per cycle. By identifying faulty chips that contain pdef's that degrade performance within some limits and binning these chips based on the their resulting instruction throughput, effective yield can be improved in a radically new manner that is completely different from the current practice of performance binning on clock frequency. To illustrate the potential benefits of this notion, we analyze the faults in the branch prediction unit of a processor. Experimental results show that every stuck-at fault in this unit is a pdef. Furthermore, 97% of these faults induce almost no performance degradation.
Starting Page	1
Ending Page	10
File Size	196805
Page Count	10
File Format	PDF
ISBN	9781424448685
ISSN	10893539
DOI	10.1109/TEST.2009.5355594
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Degradation Circuit faults Circuit testing Clocks Error correction codes Error correction Design for testability Fault detection Fabrication System performance
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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