NDLI: Power and thermal constrained test scheduling

Content Provider	IEEE Xplore Digital Library
Author	Chunhua Yao Saluja, K.K. Ramanathan, P.
Copyright Year	2009
Description	Author affiliation: Department of Electrical and Computer Engineering, University of Wisconsin-Madison, USA (Chunhua Yao; Saluja, K.K.; Ramanathan, P.)
Abstract	We propose a test scheduling algorithm that ensures the resource compatibility and satisfies both power and thermal constraints. The proposed algorithm can start a test at an arbitrary time and it has the capability of delaying a test to let a core cool down to find a valid schedule even when traditional scheduling schemes cannot find a solution. To reduce the execution time of thermal simulation, we exploit superposition principle to compute the thermal profile rapidly and accurately. We apply our scheduling algorithm to ITC'02 SoC benchmarks and the results show a remarkable improvement in the total test length over other methods, while meeting the thermal and power constraints.
Starting Page	1
Ending Page	1
File Size	326370
Page Count	1
File Format	PDF
ISBN	9781424448685
ISSN	10893539
DOI	10.1109/TEST.2009.5355630
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Processor scheduling Scheduling algorithm Computational modeling Benchmark testing Quantum computing Thermal engineering Energy consumption Temperature Cooling Design engineering
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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