NDLI: Low cost test point insertion without using extra registers for high performance design

Content Provider	IEEE Xplore Digital Library
Author	Haoxing Ren Kusko, M. Kravets, V. Yaari, R.
Copyright Year	2009
Description	Author affiliation: IBM Corporation, USA (Haoxing Ren; Kusko, M.; Kravets, V.; Yaari, R.)
Abstract	This paper presents a new approach to improve random test coverage during physical synthesis for high performance design. This new approach performs test point insertion (TPI) to improve testability of random resistant nets. Conventional test point insertion approaches add extra registers either as control points or observation points to improve controllability or observability. However, adding extra registers has many disadvantages in high performance design. It might degrade the design performance in term of power and timing. It might also end up with even worse testability. The new approach does not add any registers; instead it only uses existing signals as test points. The test points are selected from logic paths with the most timing slack and physical placement proximity. This saves silicon area, reduces power consumption, and minimizes the design changes. The new approach also automates the test insertion process by integrating it in the physical synthesis flow. The integration helps reduce design closure turn around time significantly. Production results show nearly zero performance degradation from this approach and better testability improvement as compared to a manual test point insertion approach. Furthermore, this paper proposes a novel idea of exploiting unreachable states for test point insertion. Preliminary results on this idea are also given.
Starting Page	1
Ending Page	8
File Size	244438
Page Count	8
File Format	PDF
ISBN	9781424448685
ISSN	10893539
DOI	10.1109/TEST.2009.5355747
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Degradation Timing Logic testing Performance evaluation Controllability Observability Silicon Energy consumption Automatic testing
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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