NDLI: The ARGOS project

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2015 IEEE International Test Conference (ITC)

2014 International Test Conference

2013 IEEE International Test Conference (ITC)

2012 IEEE International Test Conference

2011 IEEE International Test Conference

2010 IEEE International Test Conference

2009 International Test Conference

Table of contents

Welcome message

Steering committee and subcommittees

ITC 2008 paper awards

ITC 2009 most significant paper award

Technical program committee

ITC technical paper evaluation and selection process

Keynote address

Invited address

TTTC: Test technology technical council

2009 technical paper reviewers

Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study

Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs

Test effectiveness evaluation through analysis of readily-available tester data

Application of non-parametric statistics of the parametric response for defect diagnosis

Testing bridges to nowhere - combining Boundary Scan and capacitive sensing

$Intel^{®}$ IBIST, the full vision realized

Fast extended test access via JTAG and FPGAs

Boundary-scan adoption - an industry snapshot with emphasis on the semiconductor industry

Minimizing outlier delay test cost in the presence of systematic variability

Accurate measurement of small delay defect coverage of test patterns

Capture power reduction using clock gating aware test generation

AutoRex: An automated post-silicon clock tuning tool

Using transition test to understand timing behavior of logic circuits on $UltraSPARC^{TM}$ T2 family

Data learning techniques and methodology for Fmax prediction

Built-in EVM measurement for OFDM transceivers using all-digital DFT

Enabling GSM/GPRS/EDGE EVM testing on low cost multi-site testers

Low cost AM/AM and AM/PM distortion measurement using distortion-to-amplitude transformations

Fault diagnosis for embedded read-only memories

A novel test flow for one-time-programming applications of NROM technology

A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design

On-chip power supply noise measurement using Time Resolved Emission (TRE) waveforms of Light Emission from Off-State Leakage Current (LEOSLC)

Voltage transient detection and induction for debug and test

Cache-resident self-testing for I/O circuitry

Compression-aware pseudo-functional testing

Compression based on deterministic vector clustering of incompatible test cubes

On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment

An economical, precise and limited access In-Circuit Test method for pulse-width modulation (PWM) circuits

Augmenting board test coverage with new intel powered opens boundary scan instruction

An outlier detection based approach for PCB testing

SSC applied serial ATA signal generation and analysis by analog tester resources

A robust method for identifying a deterministic jitter model in a total jitter distribution

Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing

A timestamping method using reduced cost ADC hardware

A novel architecture for on-chip path delay measurement

Low cost test point insertion without using extra registers for high performance design

Test economics for homogeneous manycore systems

Physical defect modeling for fault insertion in system reliability test

BIST scheme for RF VCOs allowing the self-correction of the cut

A2DTest: A complete integrated solution for on-chip ADC self-test and analysis

New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testing

Thermal characterization of BIST, scan design and sequential test methodologies

Cost-effective approach to improve EMI yield loss

A development platform and electronic modules for automated test up to 20 Gbps

Microprocessor system failures debug and fault isolation methodology

Design for failure analysis inserting replacement-type observation points for LVP

Feature based similarity search with application to speedpath analysis

Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning

An ant colony optimization technique for abstraction-guided state justification

Diagnostic test generation for transition faults using a stuck-at ATPG tool

X-alignment techniques for improving the observability of response compactors

An industrial case study for X-canceling MISR

Test point insertion using functional flip-flops to drive control points

Running scan test on three pins: yes we can!

A novel array-based test methodology for local process variation monitoring

Fast circuit topology based method to configure the scan chains in Illinois Scan architecture

Structural test of power-only defects: ATPG or ad-hoc?

Using the Multiple-Clue approach for system testing on AIRBUS FAL (Final Assembly Line)

Post-silicon validation: It's the unique fails that hurt you

Structural test of power-only defects: ATPG or ad-hoc?

Using the Multiple-Clue approach for system testing on AIRBUS FAL (Final Assembly Line)

Post-silicon validation: It's the unique fails that hurt you

Tolerance of performance degrading faults for effective yield improvement

The best of both worlds: Merging the benefits of Rack&Stack and universal ATE

At-speed test on the $QorIQ^{TM}$ P2020 platform

Testing 3D chips containing through-silicon vias

Doing more with less - An IEEE 1149.7 embedded tutorial : Standard for reduced-pin and enhanced-functionality test access port and boundary-scan architecture

40 years of reliable computing at stanford CRC

The ROAR project (1997–2002)— Looking Back

The ARGOS project

Test chip experiments at stanford CRC

Can EDA help solve analog test and DFT challenges?

EDA for analog DFT? - designers must get on the bus

Testing of 3D chips: Is there anything new under the sun?

Test challenges for 3D-SICs: All the old, most of the recent, and then some new!

Implications of 3-D integrated circuits at board test position paper

Power faults - What is our tolerance for defects?

Physically aware DFT: Is it worth all the heavy lifting?

Predictive solutions for test - The next DFT paradigm?

Panel Synopsis - How (Un)affordable is true cost of test?

Panel synopsis - How (Un)affordable is true cost of test?

How (Un)affordable is the true cost of test?

Eliminating product infant mortality failures using prognostic analysis

Automatic diagnostic tool for Analog-Mixed Signal and RF load boards

Scalable and efficient integrated test architecture

Very-Low-Voltage testing of amorphous silicon TFT circuits

Low power multi-chains encoding scheme for SoC in low-cost environment

Power and thermal constrained test scheduling

Power scan: DFT for power switches in VLSI designs

IEEE P1687 IJTAG a presentation of current technology

Test Mode Entry and Exit Methods for IEEE P1581 compliant devices

A novel multisite testing techniques by using frequency synthesizer

Design-for-secure-test for crypto cores

Non-invasive RF built-in testing using on-chip temperature sensors

NAND flash testing: A preliminary study on actual defects

Built-in Self Test for Error Vector Magnitude measurement of RF transceiver

Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing

Portable simulation/emulation stimulus on an industrial-strength SoC

Test infrastructures evaluation at transaction level

Trace signal selection for debugging electrical errors in post-silicon validation

Defect coverage of non-intrusive board tests (NBT): What does it mean when a non-intrusive board test passes?

What is IEEE P1149.8.1 and why?

Manufacturing data: Maximizing value using component-to-system analysis

High Speed I/O Test Cable Assembly Interfaces for Next Generation Multi-Gigabit Serial Protocols

Test access mechanism for multiple identical cores

2008 IEEE International Test Conference

2007 IEEE International Test Conference

2006 IEEE International Test Conference

IEEE International Conference on Test, 2005.

2004 International Conferce on Test

International Test Conference, 2003. Proceedings. ITC 2003.

Proceedings. International Test Conference

Proceedings International Test Conference 2001 (Cat. No.01CH37260)

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270)

Proceedings International Test Conference 1997

Proceedings International Test Conference 1996. Test and Design Validity

Proceedings., International Test Conference

Proceedings of 1995 IEEE International Test Conference (ITC)

Proceedings International Test Conference 1992

Proceedings of IEEE International Test Conference - (ITC)

1991, Proceedings. International Test Conference

Proceedings. International Test Conference 1990

Proceedings. 'Meeting the Tests of Time'., International Test Conference

International Test Conference 1988 Proceeding@m_New Frontiers in Testing

The ARGOS project

Content Provider	IEEE Xplore Digital Library
Copyright Year	2009
Abstract	Radiation, such as alpha particles and cosmic rays, can cause transient faults in electronic systems. Such faults cause errors called Single-Event Upsets (SEUs). SEUs are a major source of errors in electronics used in space applications. There is also a growing concern about SEUs at ground level for deep submicron technologies. Radiation hardening is an effective yet costly solution to this problem. Commercial off-the-shelf (COTS) components have been considered as a low-cost alternative to radiation-hardened parts. In ARGOS project, these two approaches were compared in an actual space experiment. We assessed the effectiveness of Software-Implemented Hardware Fault Tolerance (SIHFT) techniques in enhancing the reliability of COTS.
Starting Page	1
Ending Page	1
File Size	247781
Page Count	1
File Format	PDF
ISBN	9781424448685
ISSN	10893539
DOI	10.1109/TEST.2009.5355813
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Single event transient Fault tolerance Hardware Circuit testing Circuit faults Cyclic redundancy check Space technology Cache memory Error analysis Digital circuits
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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