NDLI: Board test and ITC: what does the future hold?

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An automated methodology to diagnose geometric defect in the EEPROM cell

Diagonal test and diagnostic schemes for flash memories

Efficient embedded memory testing with APG

IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips

Integrated test data decompression and core wrapper design for low-cost system-on-a-chip testing

Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm

On testing of interconnect open defects in combinational logic circuits with stems of large fanout

Parametric failures in CMOS ICs - a defect-based analysis

Clock faults' impact on manufacturing testing and their possible detection through on-line testing

Frequency/phase movement analysis by orthogonal demodulation [mixed signal SOC testing]

A wavelet-based timing parameter extraction method

An embedded core for sub-picosecond timing measurements

Test point insertion that facilitates ATPG in reducing test time and data volume

Scan test data volume reduction in multi-clocked designs with safe capture technique

Packet-based input test data compression techniques

DFT techniques for wafer-level at-speed testing of high-speed SRAMs

A variable drivability (VD) output buffer for the system in a package (SIP) and high frequency wafer test

On-chip repair and an ATE independent fusing methodology

Integration of SRAM redundancy into production test

Verifying properties using sequential ATPG [IC design]

Combining ATPG and symbolic simulation for efficient validation of embedded array systems

Automatic generation of design constraints in verifying high performance embedded dynamic circuits

Design rewiring using ATPG

Fault tuples in diagnosis of deep-submicron circuits

A persistent diagnostic technique for unstable defects

Multiplets, models, and the search for meaning: improving per-test fault diagnosis

An effective diagnosis method to support yield improvement

Across the great divide: examination of simulation data with actual silicon waveforms improves device characterization and production test development

DUT capture using simultaneous logic acquisition

Considerations for STIL data application

Verification of device interface hardware interconnections prior to the start of testing

Embedded deterministic test for low cost manufacturing test

X-compact: an efficient response compaction technique for test cost reduction

Reducing test data volume using LFSR reseeding with seed compression

Multiscan-based test compression and hardware decompression using LZ77

Embedded memory test and repair: infrastructure IP for SOC yield

An integrated approach to yield loss characterization

Robustness IPs for reliability and security of SoCs

XIDEN: crosstalk target identification framework

Analog macromodeling of capacitive coupling faults in digital circuit interconnects

Testing cross-talk induced delay faults in static CMOS circuit through dynamic timing analysis

A new algorithm for global fault collapsing into equivalence and dominance sets

On testing high-performance custom circuits without explicit testing of the internal faults

Analysis of delay test effectiveness with a multiple-clock scheme

Realistic spring probe testing methods and results

Low contact force probing on copper electrodes

Compensation of transmission line loss for Gbit/s test on ATEs

Multi-purpose digital test core utilizing programmable logic

Complete, contactless I/O testing reaching the boundary in minimizing digital IC testing cost

Realizing the benefits of structural test for Intel microprocessors

Isolating and removing sources of variation in test data

A multi-language goal-tree based functional test planning system

System manufacturing test cost model

On-line testing of multi-source noise-induced errors on the interconnects and buses of system-on-chips

Static analysis of SEU effects on software applications

Experimental evaluation of scan tests for bridges

A set of benchmarks for modular testing of SOCs

Effective and efficient test architecture design for SOCs

On the use of k-tuples for SoC test schedule representation

Physical principles of interface design

What a device interface board really costs: an evaluation of technical considerations for testing products operating in the Gigabit region

The process and challenges of a high-speed DUT board project

Test methodology for Motorola's high performance e500 core based on PowerPC instruction set architecture

Support for debugging in the Alpha 21364 microprocessor

FRITS - a microprocessor functional BIST method

FPGA test and coverage

Fault grading FPGA interconnect test configurations

BIST-based diagnosis of FPGA interconnect

Facilitating rapid first silicon debug

Core-based scan architecture for silicon debug

Re-using DFT logic for functional and silicon debugging test

The manic depression of microprocessor debug

Silicon symptoms to solutions: applying design for debug techniques

Screening minVDD outliers using feed-forward voltage testing

Wafer-level defect-based testing using enhanced voltage stress and statistical test data evaluation

Redundancy implications for early-life reliability: experimental verification of an integrated yield-reliability model

Jitter testing for multi-Gigabit backplane SerDes - techniques to decompose and combine various types of jitter

On the accuracy of jitter separation from bit error rate function

A new method for testing jitter tolerance of SerDes devices using sinusoidal jitter

A scalable, low cost design-for-test architecture for UltraSPARC/spl trade/ chip multi-processors

Optimal BIST using an embedded microprocessor

An implementation of IEEE 1149.1 to avoid timing violations and other practical in-compliance improvements

A structured graphical tool for analyzing boundary scan violations

Improved digital I/O ports enhance testability of interconnections

Testing finite state machines based on a structural coverage metric

An efficient linear time algorithm for scan chain optimization and repartitioning

Integrating DFT in the physical synthesis flow

Power driven chaining of flip-flops in scan architectures

Automatic scan insertion and test generation for asynchronous circuits

RTL level preparation of high-quality/low-energy/low-power BIST

An ATPG for threshold testing: obtaining acceptable yield in future processes

Generation of low power dissipation and high fault coverage patterns for scan-based BIST

Scan power reduction through test data transition frequency analysis

Implementation of model-based testing for medium- to high-resolution Nyquist-rate ADCs

A new test generation approach for embedded analogue cores in SoC

Test setup simulation - a high-performance VHDL-based virtual test solution meeting industrial requirements

Use of pipeline converters for ATE applications

R4X/D4X-formatters for flexible test system architecture

CMOS circuit technology for precise GHz timing generator

New paradigm for signal paths in ATE pin electronics are needed for serialcom device testing

High current DPS architecture for sort test challenge

A novel fault injection method for system verification based on FPGA boundary scan architecture

Efficient design of system test: a layered architecture

Intelligent agents and BIST/BISR - working together in distributed systems

Charge based transient current testing (CBT) for submicron CMOS SRAMs

Improved I/sub DDQ/ testing with empirical linear prediction

Comparison of I/sub DDQ/ testing and very-low voltage testing

Finding a small set of longest testable paths that cover every gate

Techniques to reduce data volume and application time for transition test

On identifying indistinguishable path delay faults and improving diagnosis

Application of high-quality built-in test to industrial designs

Pseudo random patterns using Markov sources for scan BIST

Test and evaluation of multiple embedded mixed-signal test cores

High accuracy stimulus generation for A/D converter BIST

Evaluating ATE features in terms of test escape rates and other cost of test culprits

Wafer/package test mix for optimal defect detection

IEEE P1149.6: a boundary-scan standard for advanced digital networks

Test coverage: what does it mean when a board test passes?

Built-in self test of CMOS-MEMS accelerometers

Incremental diagnosis of multiple open-interconnects

Signal integrity loss in SoC's interconnects: a diagnosis approach using embedded microprocessor

Hierarchical data invalidation analysis for scan-based debug on multiple-clock system chips

Use of DFT techniques in speed grading a 1 GHz+ microprocessor

Scan-based transition fault testing - implementation and low cost test challenges

A DFT technique for low frequency delay fault testing in high performance digital circuits

WCDMA testing with a baseband/IF range AWG

Testing wireless local area network transceiver ICs at 5GHz

Architecting millisecond test solutions for wireless phone RFICs

Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints

Adapting an SoC to ATE concurrent test capabilities

Dedicated autonomous scan-based testing (DAST) for embedded cores

Neighbor selection for variance reduction in I/sub DDQ/ and other parametric data

Test coverage models for system test?

Can IC test learn from how a tester is tested

What can IC test teach system test?

Is it rocket science?

TAPS all over my chip! So now what do I do?

Inevitable use of TAP domains in SOCs

Position statement: TAPs all over my chips

TAPs all over my chips

Good scan = good quality level? Well, it depends

Scan and BIST can almost achieve test quality levels

Is scan (alone) sufficient to test today's microprocessors? Not quite, but we can't get the job done without it

Scan-based testing: the only practical solution for testing ASIC/consumer products

Trouble with scan

A/MS BISTs: the facts, just the facts

Mixed-signal BIST: fact or fiction

Mixed signal BIST: fact or fiction

Mixed-signal BIST: fact or fiction

IC mixed-signal BIST: separating facts from fiction

Mission impossible? Open architecture ATE

Mission possible? Open architecture ATE

Is an open architecture tester really achievable?

The consequences of an open ATE architecture

An open architecture for semiconductor test: enablers and challenges

Open ATE architecture: key challenges

The role of test in a highly outsourced business model

The yield of test outsourcing

The impact of outsourcing on test

Outsourcing test without standards?

Test and repair of embedded flash memories

Test time impact of redundancy repair in embedded flash memory

Test and repair of non-volatile commodity and embedded memories (NAND flash memory)

Selective optimization of test for embedded flash memory

Test and repair of non-volatile commodity and embedded memories

Testing highly integrated wireless circuits and systems with low cost tester: how to overcome the challenge?

Wireless SOC testing: Can RF testing costs be reduced?

GHz testing and its fuzzy targets

Multi-GHz interface devices should be tested using external test resources

Challenges and solutions for multi-Gigahertz testing

Multi Gigahertz digital test challenges and techniques

On-die DFT based solutions are sufficient for testing multi-GHz interfaces in manufacturing (and are also key to enabling lower cost ATE platforms)

Pervasive multi Giga bit links - an ATE challenge?

Board test and ITC: what does the future hold?

Is board test worth talking about?

Board test: wanted dead or alive

Is ITC bored with board test?

Board test is not mature

Panel: "board test and ITC: what does the future hold?"

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Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270)

Proceedings International Test Conference 1997

Proceedings International Test Conference 1996. Test and Design Validity

Proceedings., International Test Conference

Proceedings of 1995 IEEE International Test Conference (ITC)

Proceedings International Test Conference 1992

Proceedings of IEEE International Test Conference - (ITC)

1991, Proceedings. International Test Conference

Proceedings. International Test Conference 1990

Proceedings. 'Meeting the Tests of Time'., International Test Conference

International Test Conference 1988 Proceeding@m_New Frontiers in Testing

Board test and ITC: what does the future hold?

Content Provider	IEEE Xplore Digital Library
Author	Bennetts, R.G.
Copyright Year	2002
Description	Author affiliation: Bennetts Associates (Bennetts, R.G.)
Abstract	Summary form only given. The purpose of this panel is to explore the status of board test totry to find out if it has become stagnant or not, and to identify the future role, if any, of ITC with respect to board test topics. Panelists will be drawn from chip and board test experts, plus those who can remember when board test was a much larger part of ITC. As a loyal uficionudo of ITC, I very much hope that the panel will re-state the need for more exposure to board test problems and solutions, and re-energize ITC's interest in the subject. A record of the panel discussion was not made available for publication as part of the conference proceedings.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council IEEE Philadelphia Sect
Starting Page	1234
Ending Page	1234
File Size	78872
Page Count	1
File Format	PDF
ISBN	0780375424
ISSN	10893539
DOI	10.1109/TEST.2002.1041935
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-10-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic testing Manufacturing Switches Prototypes System testing Backplanes Technological innovation Semiconductor device measurement Delay Packaging
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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