NDLI: X-compact: an efficient response compaction technique for test cost reduction

Content Provider	IEEE Xplore Digital Library
Author	Mitra, S. Kee Sup Kim
Copyright Year	2002
Description	Author affiliation: Intel Corp., Sacramento, CA, USA (Mitra, S.; Kee Sup Kim)
Abstract	We present a technique for compacting test response data using combinational logic circuits. Our compaction technique enables up to an exponential reduction in the number of pins required to collect test response from a chip. The combinational circuits require negligible area, do not add any extra delay during normal operation, guarantee detection of defective chips even in the presence of sources of unknown logic values (often referred to as Xs) and preserve diagnosis capabilities for all practical scenarios. The technique has minimum impact on current design and test flows, and can be used to reduce test time, test data volume, test-I/O pins and tester channels, and also to improve test quality.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council IEEE Philadelphia Sect
Starting Page	311
Ending Page	320
File Size	666054
Page Count	10
File Format	PDF
ISBN	0780375424
ISSN	10893539
DOI	10.1109/TEST.2002.1041774
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-10-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Compaction Costs Pins Circuit testing Flip-flops Combinational circuits Logic testing Design for testability Clocks Added delay
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in