NDLI: Virtual prototyping for PPM-level failures in microelectronic packages

Content Provider	IEEE Xplore Digital Library
Author	van Driel, W.D. Engelen, R.A.B. Mavinkurve, A. Cobussen, H. van Dort, M. van Eckendonk, M. Endrinal, L.
Copyright Year	2009
Description	Author affiliation: Phillips Applied Technologies, Eindhoven, The Netherlands (Engelen, R.A.B.) \|\| NXP Semiconductors, Nijmegen, The Netherlands (van Driel, W.D.; Mavinkurve, A.; Cobussen, H.; van Dort, M.; van Eckendonk, M.; Endrinal, L.)
Abstract	In this paper, the interaction between chip and package is investigated with the focus on low ppm-level failures. More specifically, the failure mode of inter-metal shorts is investigated, caused by either electrical discharges (ESD) or internal/external mechanical forces. It is demonstrated that forces induced by the filler particles in the molding compound can cause these shorts. Finite element simulations are performed in order to estimate the stress levels in the backend stack of the integrated circuit (IC). Nano-indentation experiments are performed to measure the hardness of different passivation materials. The simulation and indentation results are combined with estimations and measurements of the particle size distribution, flow modeling and statistical methods. As such, the ppm-level of the failures could be attributed to the low chance that a filler particle would land on the critical location. Measures to prevent these failures are to be found in the area of improved passivation materials and/or recipes in combination with other molding compounds. For successful development of IC backend structures and processes, it is essential to take into account the influence of the package in the earlier phase of IC backend development.
Starting Page	1
Ending Page	5
File Size	9797551
Page Count	5
File Format	PDF
ISBN	9781424441600
DOI	10.1109/ESIME.2009.4938446
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-26
Publisher Place	The Netherlands
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Virtual prototyping Microelectronics Packaging Circuit simulation Integrated circuit measurements Passivation Electrostatic discharge Finite element methods Stress Performance evaluation
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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