NDLI: Effects of geometry and material properties for stacked IC package with spacer structure

Content Provider	IEEE Xplore Digital Library
Author	Ming-Che Hsieh Chih-Kung Yu Wei Lee
Copyright Year	2009
Description	Author affiliation: EOL/Industrial Technology Research Institute, Rm.168, Bldg.14, No.195, Sec. 4, Chung Hsing Road, Chutung, Hsinchu, Taiwan 31040, R.O.C. (Ming-Che Hsieh; Chih-Kung Yu; Wei Lee)
Abstract	As the electronic industry is making its progress to miniaturize high performance, smaller and lower-priced IC packages, 3D packaging technologies are presently used to achieve these goals. Although 3D packaging technologies are vastly studied and applied to perform better performance, low power consumption and smaller packaging size of IC packages, thermo-mechanical problems occur as well due to the 3D stacking feature. Because chips are vertically stacking in 3D packages, higher thermal resistances are resulted and their corresponding induced thermal stresses and heat dissipations are becoming major reliability concerns. In order to realize thermal stresses distributions in stacked IC packages with spacer structures, the three dimensional finite element analysis (FEA) modeling has been employed. For the purpose of studying effects of geometry and material properties of stacked IC package with spacer structure, several comparisons of variations of geometry and materials are discussed in this paper. Through these comparisons, effects of material properties of spacer structures in stacked IC packages and those resulted in stresses distributions of copper TSV (through-silicon-vias), dies and spacers can be presented. Moreover, effects of geometry of die and copper TSV size, die stacking number, TSV distributions as well as TSV/bump pitch and spacer/bump thickness are also illustrated. These results will be helpful design guidelines to engineers if optimization designs for stress solutions in stacking IC package with spacer structure are needed.
Starting Page	1
Ending Page	6
File Size	15731638
Page Count	6
File Format	PDF
ISBN	9781424441600
DOI	10.1109/ESIME.2009.4938410
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-26
Publisher Place	The Netherlands
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Geometry Material properties Integrated circuit packaging Electronic packaging thermal management Thermal stresses Stacking Through-silicon vias Space technology Thermal resistance Integrated circuit modeling
Content Type	Text
Resource Type	Article

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