NDLI: A novel FPGA implementation of mirror-paradigm RS-based QC-LDPC decoder for NVM channels

Content Provider	IEEE Xplore Digital Library
Author	Lim, M.H.L. Wang Ling Goh Zhiliang Qin
Copyright Year	2012
Description	Author affiliation: School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore (Lim, M.H.L.; Wang Ling Goh) \|\| Data Storage Institute, Agency for Science, Technology and Research, Singapore (Zhiliang Qin)
Abstract	The scrutiny of the class of Reed-Solomon (RS) based quasi-cyclic (QC) low-density parity-check (LDPC) codes has inspired the authors to propose a memory efficient mirror-paradigm (MP) RS-based QC-LDPC code by exploiting the geometrical properties from the RS-based QC-LDPC nomenclature. Without any loss in performance, the proposed MPRS-based QC-LDPC code delivers discernible memory savings that address the concerns of hefty H-matrices associated to lengthy codewords for non-volatile memory (NVM) applications. Besides, the MPRS-based QC-LDPC codes are not confined to any particular hardware implementation and are compatible with various decoder architectures to complement other optimization schemes.
Starting Page	760
Ending Page	765
File Size	243428
Page Count	6
File Format	PDF
ISBN	9781467350839
e-ISBN	9781467350822
e-ISBN	9781467350815
DOI	10.1109/ISPACS.2012.6473593
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-04
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Generators Decoding Parity check codes Nonvolatile memory Memory management Vectors Polynomials non-volatile memory(NVM) Reed-Solomon(RS) low-density parity-check(LDPC) codes mirror-paradigm(MP)
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A novel method of constructing Quasi-Cyclic RS-LDPC codes for 10GBASE-T Ethernet

High-throughput dual-shift stochastic-detection quasi-cyclic LDPC decoder

Cost-effective scalable QC-LDPC decoder designs for non-volatile memory systems

Efficient Reed-Solomon based LDPC decoders

Efficient memory optimization and high throughput decoding architecture based on LDPC codes

Memory efficient FPGA implementation for flooded LDPC decoder

A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes

A memory efficient fpga implementation of quasi-cyclic ldpc decoder.

bit-serial approximate minsum LDPC decoder and FPGA implementation (2006)

A novel FPGA implementation of mirror-paradigm RS-based QC-LDPC decoder for NVM channels

Similar Documents

A novel method of constructing Quasi-Cyclic RS-LDPC codes for 10GBASE-T Ethernet

High-throughput dual-shift stochastic-detection quasi-cyclic LDPC decoder

Cost-effective scalable QC-LDPC decoder designs for non-volatile memory systems

Efficient Reed-Solomon based LDPC decoders

Efficient memory optimization and high throughput decoding architecture based on LDPC codes

Memory efficient FPGA implementation for flooded LDPC decoder

A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes

A memory efficient fpga implementation of quasi-cyclic ldpc decoder.

bit-serial approximate minsum LDPC decoder and FPGA implementation (2006)

A novel FPGA implementation of mirror-paradigm RS-based QC-LDPC decoder for NVM channels