NDLI: Power-saving analysis of adiabatic logic in subthreshold region

Content Provider	IEEE Xplore Digital Library
Author	Takahashi, Y. Sekine, T. Nayan, N.A. Yokoyama, M.
Copyright Year	2012
Description	Author affiliation: Department of Electrical and Electronic, Faculty of Engineering, Gifu University, Japan, 1-1 Yanagido, Gifu-shi, 501-1193 (Takahashi, Y.; Sekine, T.) \|\| Graduate School of Science and Engineering, Yamagata University, Japan, 4-3-16 Jonan, Yonezawa-shi, 992-8510 (Yokoyama, M.) \|\| Department of Electrical, Electronic and Systems Engineering, Faculty of Engineering and Built Environment, National University of Malaysia, 43600 UKM Bangi, Selangor, Malaysia (Nayan, N.A.)
Abstract	This paper reports a comparison of energy dissipation between different adiabatic logics in the subthreshold operation. In SPICE simulation we use a real industrial 0.18 μm BSIM3v3 model having a device parameter in the subthreshold region and then confirm the energy savings of quasi-adiabatic logic families, namely, 2N2N2P, 2PC2AL, CAL, ECRL, PAL, PECRL, PFAL, and SAL. From the results we show that the energy consumption of our previously proposed 2PC2AL inverter is lower than those of the other adiabatic logics, in the range of from 10 kHz to 10 MHz.
Starting Page	590
Ending Page	594
File Size	240307
Page Count	5
File Format	PDF
ISBN	9781467350839
e-ISBN	9781467350822
e-ISBN	9781467350815
DOI	10.1109/ISPACS.2012.6473558
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-04
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks CMOS integrated circuits Inverters Logic gates Energy dissipation Transistors Power supplies smart card adiabatic logic subthreshold logic low power RFID
Content Type	Text
Resource Type	Article

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