NDLI: A 300 mV 10 MHz 4 kb 10T subthreshold SRAM for ultralow-power application

Content Provider	IEEE Xplore Digital Library
Author	Wei-Bin Yang Chi-Hsiung Wang I-Ting Chuo Huang-Hsuan Hsu
Copyright Year	2012
Description	Author affiliation: Department of Electrical Engineering Tamkang University Tamsui, Taipei, Taiwan (Wei-Bin Yang; Chi-Hsiung Wang; I-Ting Chuo; Huang-Hsuan Hsu)
Abstract	Ultralow-power devices have become popular in recent years because of their use in a number of applications, such as medical devices and communications. For ultralow-power consideration, the crucial factors in SRAMs are stability and reliability. A number of researchers considered various configurations of bit-cells for SRAMs for subthreshold operations, with differential pair structure and single-ended 8T, 9T, and 10T to improve stability and reliability. This paper proposes a 10T differential bit-cell that can effectively separate the read and write operation paths. We used a high Vth NMOS in the write operation path to reduce the bit-line leakage current. We also used virtual ground (V_Vss) to reduce the bit-line leakage to ensure that the data can be read correctly. The proposed SRAM was composed of 16 blocks, and each block had four columns and 64 cells per bit-line in a column. This study implemented a 4 kb 10T subthreshold SRAM in 90 nm CMOS technology operating at 10 MHz and 300 mV, which exhibited power consumption of 4.25 μW and energy consumption of 0.85 pJ for one write and one read operation.
Starting Page	604
Ending Page	608
File Size	408492
Page Count	5
File Format	PDF
ISBN	9781467350839
e-ISBN	9781467350822
e-ISBN	9781467350815
DOI	10.1109/ISPACS.2012.6473561
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-04
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS integrated circuits Power demand CMOS technology SRAM cells Circuit stability MOS devices Ultralow-Power SRAM Subthreshold
Content Type	Text
Resource Type	Article

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