NDLI: High-throughput dual-shift stochastic-detection quasi-cyclic LDPC decoder

Content Provider	IEEE Xplore Digital Library
Author	Lim, M.H.L. Wang Ling Goh
Copyright Year	2013
Description	Author affiliation: Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore (Lim, M.H.L.; Wang Ling Goh)
Abstract	Driven by its renowned near-capacity performance over a wide spectrum of channels, the capitalization of quasi-cyclic low-density parity-check (QC-LDPC) codes is irrefutably the focal point of research and solution to virtually all communication systems of the next generation. Steered towards non-volatile memory (NVM) storage applications, we introduce a modernistic approach to LDPC decoding in this paper, known as the dual-shift stochastic-detection (DSSD). Weaving two novel ideas: dual-shift cyclic generation and stochastic-detection of local minima, our proposed DSSD decoder achieves throughput gains (~ 300%) by minimizing its overall computational delay and maximizing its operational frequency. Along with the amalgamation of our spearheading mirror-paradigm, the DSSD QC-LDPC decoder acquires yet another dimension of gain in throughput while relinquishing a cluster of its address generation counters, which elicits a wide expanse for its application.
Starting Page	1
Ending Page	5
File Size	131819
Page Count	5
File Format	PDF
e-ISBN	9781479904341
DOI	10.1109/ICICS.2013.6782970
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-10
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Throughput Parity check codes Decision support systems Delays Indexes Clocks Reed-Solomon (RS) codes dual-shift stochastic-detection (DSSD) FPGA high-throughput decoder low-density parity-check (LDPC) codes quasi-cyclic (QC) codes
Content Type	Text
Resource Type	Article

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