NDLI: Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors

Content Provider	IEEE Xplore Digital Library
Author	Fengwei An Mihara, K. Yamasaki, S. Lei Chen Mattausch, H.J.
Copyright Year	2015
Description	Author affiliation: Hiroshima Univ., Higashi-Hiroshima, Japan (Fengwei An; Mihara, K.; Yamasaki, S.; Lei Chen; Mattausch, H.J.)
Abstract	Apart from the speed performance, a common IC-implementation problem for nearest neighbor search, one of the most basic algorithms in pattern recognition, is low flexibility to different task applications. We report a digital word-parallel as sociative memory architecture with reconfigurable storage-space of reference vectors and clock-counting-based nearest-Euclidean-distance search, enabling single-chip implementation of k-nearest-neighbor (kNN) classification and configuration for m any different applications. The main time-consuming part of kNN, the clock-based minimal-distance searching, is carried out by weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear in crease. This clock-based search concept achieves thus high classification speed, good area-efficiency and low power dissipation. In general, an IC implementation has limited flexibility after manufacturing. The proposed programmable switching circuits, which are located between groups of vector components, enable flexibility of reference feature-vector dimension and number at the same time. After k minimal distance searching, a dedicated circuit for majority vote is used to assign the unknown input to the class with the highest vote value. A test chip in 180 nm CMOS technology, which has 32 rows, 4 elements in each row and 2 8-bit components in each element, achieves low power dissipation of 61.4 mW (at 45.58 MHz and 1.8 V). In particular, the reconfigurable distance search circuit consumes only 11.9 mW.
Starting Page	1
Ending Page	4
File Size	336378
Page Count	4
File Format	PDF
ISBN	9781467371919
DOI	10.1109/ASSCC.2015.7387456
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-09
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Clocks Radiation detectors Logic gates Associative memory Multiplexing Power dissipation majority vote reconfigurable associative memory clock-based nearest-distance search k nearest neighbor
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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