NDLI: An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Meng Li Weijers, J.-W. Derudder, V. Vos, I. Rykunov, M. Dupont, S. Debacker, P. Dewilde, A. Yanxiang Huang Van der Perre, L. Van Thillo, W.
Copyright Year	2015
Description	Author affiliation: Perceptive Syst. Dept., IMEC, Leuven, Belgium (Meng Li; Weijers, J.-W.; Derudder, V.; Vos, I.; Rykunov, M.; Dupont, S.; Debacker, P.; Dewilde, A.; Yanxiang Huang; Van der Perre, L.; Van Thillo, W.)
Abstract	The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of transformation towards 5G. An energy efficient 18Gbps LDPC decoder based on LDPC ASIP with half layer paralleled architecture is proposed. The feasibility of the design is proven by its demonstrator silicon in 28nm CMOS technology, with a record energy efficiency of 18.4 pJ/decoded bit and area efficiency of 23.8 $Gbps/mm^{2}$ for the ½ coding rate working at 18.4Gbps. With frequency, voltage scaling and multi-core management, the decoder supports a wide range of throughput, from 1.8Gbps to 18.4Gbps. The measurement results show the ASIP based design not only provides an energy efficient high speed solution but also be competitive with published ASIC solution at low and medium throughput scenarios.
Starting Page	1
Ending Page	5
File Size	579662
Page Count	5
File Format	PDF
ISBN	9781467371919
DOI	10.1109/ASSCC.2015.7387473
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-09
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Throughput Parity check codes Encoding Energy efficiency Standards Computer architecture processor LDPC 802.11ad
Content Type	Text
Resource Type	Article

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