NDLI: Word-parallel coprocessor architecture for digital nearest Euclidean distance search

Content Provider	IEEE Xplore Digital Library
Author	Akazawa, T. Sasaki, S. Mattausch, H.J.
Copyright Year	2013
Description	Author affiliation: Res. Inst. for Nanodevice & Bio Syst., Hiroshima Univ., Hiroshima, Japan (Akazawa, T.; Sasaki, S.; Mattausch, H.J.)
Abstract	The reported digital, word-parallel and scalable coprocessor architecture for nearest Euclidean distance (ED) search is based on mapping the distance into time domain onto an equivalent clock number. Area-efficient sequential square calculation and a minimization algorithm of the clock number necessary for the search are applied for practical efficiency. Experimental concept verification was done with an 180nm CMOS design implementing 32 reference vectors with 16 components and 8 bit per component. The fabricated test chips achieved 1.19μs average search time, 5.77 μs worst-case search time and low power dissipation of 8.75mW at 47MHz and Vdd=1.8V for code-book-based picture compression. To our best knowledge this is the first report of practical, word-parallel, digital nearest ED-search architecture. In comparison to previous digital-analog ASIC and GPU implementations, factors 1.8 and $4.5·10^{5}$ smaller power delay products per 1NN search are realized, respectively.
Starting Page	267
Ending Page	270
File Size	670523
Page Count	4
File Format	PDF
ISBN	9781479906437
ISSN	19308833
e-ISBN	9781479906451
DOI	10.1109/ESSCIRC.2013.6649124
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-16
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Vectors CMOS integrated circuits Coprocessors Euclidean distance Data compression Radiation detectors
Content Type	Text
Resource Type	Article

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