NDLI: A 1V fractional-N PLL with nonlinearity-insensitive modulator

Please wait, while we are loading the content...

2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)

IC challenges in 5G

Silicon systems security and building a root of trust

A cell current compensation scheme for 3D NAND FLASH memory

0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications

A 1.74mW/GHz 0.11–2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers

A 7T-SRAM with data-write technique by capacitive coupling

A THz signal source with integrated antenna for non-destructive testing in 28nm bulk CMOS

A fully-integrated 860-GHz CMOS terahertz sensor

A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS

CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS

A K-band pulse radar transceiver with highly digital closed-loop time-of-flight measurement

A fully integrated self-oscillating switched-capacitor DC-DC converter for near-threshold loads

A 130dB PSRR, 108dB DR and 95dB SNDR, ground-referenced audio decoder with PSRR-enhanced load-adaptive Class-G 16Ohm headphone amplifiers

A calibration-free time difference accumulator using two pulses propagating on a single buffer ring

A 2800-μm2 thermal-diffusivity temperature sensor with VCO-based readout in 160-nm CMOS

A 0.45 V, 15.6 nW MOSFET-only sub-threshold voltage reference with no amplifiers

A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS

A 1V fractional-N PLL with nonlinearity-insensitive modulator

A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS

A 12.77-MHz on-chip relaxation oscillator with digital compensation for loop delay variation

A digital bang-bang phase-locked loop with bandwidth calibration

Standing wave based clock distribution technique with application to a 10 × 11 Gbps transceiver in 28 nm CMOS

A spread-spectrum clock generator with FIR-embedded binary phase detection and 1-bit high-order ΔΣ modulation

A 1.9nJ/pixel embedded deep neural network processor for high speed visual attention in a mobile vision recognition SoC

A 400-MHz wireless neural signal processing IC with 625× on-chip data reduction and reconfigurable BFSK/QPSK transmitter based on sequential injection locking

A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm

Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors

Wavelength locking of a Si ring modulator using an integrated drop-port OMA monitoring circuit

200nA low quiescent current deep-standby mode in 28nm DC-DC buck converter for active implantable medical devices

A ZVS CMOS active diode rectifier with voltage-time-conversion delay-locked loop for wireless power transmission

A 7.6mW 2Gb/s proximity transmitter for smartphone-mirrored display applications

Dedicated ICs for wearable body sound monitoring

A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer

A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation

A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers

A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm

A 0.11mm⁁2 150mW 10GBase-T transmitter in 28nm CMOS process

A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS

A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS

A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking

A 550–2260MHz self-adjustable clock generator in 28nm FDSOI

A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy

An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS

A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors

Reconfigurable self-timed regenerators for wide-range voltage scaled interconnect

A μNMR CMOS transceiver using a butterfly-coil input for integration with a digital microfluidic device inside a portable magnet

A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process

A pulse-width-adaptive active charge balancing circuit with pulse-insertion based residual charge compensation and quantization for electrical stimulation applications

A 95% accurate EEG-connectome processor for a mental health monitoring system

An 8-channel chopper-stabilized analog front-end amplifier for EEG acquisition in 65-nm CMOS

A digital low drop-out regulator with wide operating range in a 16nm FinFET CMOS process

A fully isolated delta-sigma ADC for shunt based current sensing

A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU

A 1V 9pA analog front end with compressed sensing for electrocardiogram monitoring

A 24-bit multi-functional sensor analog front end employing low noise biasing technique with 8.2nV/√Hz input referred noise

A fully-integrated, high-conversion-ratio and dual-output voltage boost converter with MPPT for low-voltage energy harvesting

An undershoot/overshoot-suppressed current-mode buck converter with voltage-setting control for type-II compensator

A folding dickson-based fully integrated wide input range capacitive DC-DC converter achieving Vout/2-resolution and 71% average efficiency

Pseudo AC current synthesizer and DC offset-corrected technique in constant-on-time control buck converter for werable electronics

A 0.6 V–2.4 V input, fully integrated reconfigurable switched-capacitor DC-DC converter for energy harvesting sensor tags

Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS

A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise

A 1.7–2.1GHz +23dBm TX power compatible blocker tolerant FDD receiver with integrated duplexer in 28nm CMOS

A 5.2-GHz full-integrated RF front-end by T/R switch, LNA, and PA co-design with 3.2-dB NF and +25.9-dBm output power

A 2.4GHz low-power SAW-less receiver for SoC coexistence

A 180nm CMOS wireless transceiver by utilizing guard band for narrowband IoT applications

A wide-band divide-by-3 injection-locked frequency divider using tunable MOS resistor

A 2.89-μW clockless wireless dry-electrode ECG SoC for wearable sensors

A mixed-signal ASIC for triple-chamber cardiac pacemakers with heart resistance measurement

99.4% peak audio signal recovery rate and ultra-low 0.32dB matching error with 10Hz high resolution filter fitting wearable aided speech compensation system

A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS

A 132dB DR readout IC with pulse width modulation for IR focal plane arrays

Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs

A multi-path CMOS Hall sensor with integrated ripple reduction loops

A 0.57°/h bias instability 0.067°/√h angle random walk MEMS gyroscope with CMOS readout circuit

A 12-bit 104-MS/s SAR ADC in 28nm CMOS for digitally-assisted wireless transmitters

A 13-MHz 68-dB SNDR CTDSM using SAB loop filter and interpolating flash quantizer with random-skip IDWA function in 90-nm CMOS

A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW

A 1-V 9.8-ENOB 100-kS/s single-ended SAR ADC with symmetrical DAC switching technique for neural signal acquisition

124-GHz CMOS quadrature voltage-controlled oscillator with fundamental injection locking

A 25–102GHz 2.81–5.64mW tunable divide-by-4 in 28nm CMOS

220GHz wide-band MEMS switch in standard BiCMOS technology

Flicker noise upconversion mechanisms in K-band CMOS VCOs

How future mobility meets IT: Cyber-physical system designs revisit semiconductor technology

Fast memory and storage architectures for the big data era

Asian strategy for the future of semiconductor technology [panel discussion]

Table of contents

Welcome message

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

2012 IEEE Asian Solid State Circuits Conference (A-SSCC)

IEEE Asian Solid-State Circuits Conference 2011

2010 IEEE Asian Solid-State Circuits Conference

2009 IEEE Asian Solid-State Circuits Conference

2008 IEEE Asian Solid-State Circuits Conference

2007 IEEE Asian Solid-State Circuits Conference

2006 IEEE Asian Solid-State Circuits Conference

2005 IEEE Asian Solid-State Circuits Conference

A 1V fractional-N PLL with nonlinearity-insensitive modulator

Content Provider	IEEE Xplore Digital Library
Author	Yi-Chieh Huang Che-Fu Liang Ping-Ying Wang
Copyright Year	2015
Description	Author affiliation: MediaTek Inc., Hsinchu, Taiwan (Yi-Chieh Huang; Che-Fu Liang; Ping-Ying Wang)
Abstract	A 1V fractional-N PLL is proposed in 40nm technology. With modified VCO, it can be operated under 1V supply with wide tuning range and low supply sensitivity. Besides, conventional 3rd MASH SDM is sensitive to nonlinearity caused by analog path, generating in-band fractional spur that cannot be filtered by PLL loop. In order to lower the sensitivity to nonlinearity, a new type of modulator is proposed. Theorem derivation and simulation results show that this modulator is insensitive to 2nd-5th order nonlinearity. The measured in-band worst-case fractional and reference spur are -64.5dBc and -81dBc, respectively. The RMS jitter is 3.91ps under 5.85mW power consumption.
Starting Page	1
Ending Page	4
File Size	604084
Page Count	4
File Format	PDF
ISBN	9781467371919
DOI	10.1109/ASSCC.2015.7387447
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-09
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Frequency measurement Frequency modulation Voltage-controlled oscillators Sensitivity Phase modulation Sigma Delta Modulator Fractional-N PLL Fractional Spur Linearity
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in