NDLI: A 44.9% PAE digitally-assisted linear power amplifier in 40 nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Haoyu Qian Silva-Martinez, J.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA (Haoyu Qian; Silva-Martinez, J.)
Abstract	This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA segments are switched on and off according to signal power, i.e. the proposed scheme makes the PA power consumption correlate with the power of the input signal. Binary power gain variations due to segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the trade-off between efficiency and linearity by employing the digital predistortion technique. The PA is implemented in 40 nm CMOS process, it delivers a saturated output power of 35 dBm with 44.9% power-added efficiency (PAE) and linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at ±5 MHz at a maximum linear output power of 31 dBm for a baseband WCDMA signal is -35.8 dBc.
Starting Page	349
Ending Page	352
File Size	229778
Page Count	4
File Format	PDF
ISBN	9781479940905
e-ISBN	9781479940899
DOI	10.1109/ASSCC.2014.7008932
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-10
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Transistors CMOS integrated circuits Baseband Radio frequency Gain Power generation
Content Type	Text
Resource Type	Article

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