NDLI: A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW $0.0153-mm^{2}$ all-digital delay-locked loop in 65-nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Chun-Yuan Cheng Jinn-Shyan Wang Pei-Yuan Chou Shiou-Ching Chen Chi-Tien Sun Yuan-Hua Chu Tzu-Yi Yang
Copyright Year	2014
Description	Author affiliation: Dept. of EE & SoC/AIM-HI Centers, Nat. Chung Cheng Univ., Chiayi, Taiwan (Chun-Yuan Cheng; Jinn-Shyan Wang; Pei-Yuan Chou; Shiou-Ching Chen) \|\| Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan (Chi-Tien Sun; Yuan-Hua Chu; Tzu-Yi Yang)
Abstract	It is challenging to design a closed-loop all-digital delay-locked loop (ADDLL) that also has a small area, low power, and fast locking for a wide frequency range operation. In this work a cyclic half-delay-line architecture with the same type of delay lines for cyclic delay deduction and coarse locking is proposed to achieve the design goals of small area and fast locking for a wide frequency range operation. In addition to clock gating, which is used to reduce power consumption in the lock-in state regardless of the clock frequency, automatic bypassing of the cyclic operation is developed to reduce power consumption for high-frequency operations. Based on these proposed techniques, a 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW $0.0153-mm^{2}$ closed-loop ADDLL is realized in 65-nm CMOS.
Starting Page	361
Ending Page	364
File Size	1547684
Page Count	4
File Format	PDF
ISBN	9781479940905
e-ISBN	9781479940899
DOI	10.1109/ASSCC.2014.7008935
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-10
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Delays Power demand Radiation detectors Delay lines Jitter CMOS integrated circuits low power ADDLL wide range small area
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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