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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yuan Liang Nan Li Fei Wei Yu Hao Xiuping Li Junfeng Zhao Wei Yang Yuangang Wang |
| Copyright Year | 2015 |
| Description | Author affiliation: Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore (Yuan Liang; Nan Li; Fei Wei; Yu Hao) || Huawei Technol. Co., Ltd., Hangzhou, China (Junfeng Zhao; Wei Yang; Yuangang Wang) || Sch. of Electron. Eng., Beijing Univ. of Posts & Telecommun., Beijing, China (Xiuping Li) |
| Abstract | A digitally-assisted CMOS 60GHz PA is reported with high output power and improved power efficiency during power back-off. To combine large number of CMOS power transistors within compact area, a 2D distributed in-phase power combiner is utilized. Moreover, digitally-assisted self-tuning biasing is introduced for power back-off efficiency improvement, where DC power is reduced along with output power. One digitally-assisted 4-way power-combined PA prototype was implemented in 65nm CMOS process with measured output power of 17.2dBm, PAE of 11.3%, and up to 170~190% efficiency improvement during power back-off for the entire 7GHz band at 60GHz. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 2636376 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479982752 |
| DOI | 10.1109/MWSYM.2015.7166918 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-05-17 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | CMOS integrated circuits Lead |
| Content Type | Text |
| Resource Type | Article |
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