NDLI: A DC-46Gb/s 2:1 multiplexer and source-series terminated driver in 20nm CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Jian Hong Jiang Parikh, S. Lionbarger, M. Nedovic, N. Yamamoto, T.
Copyright Year	2014
Description	Author affiliation: Fujitsu Labs. of America, Sunnyvale, CA, USA (Jian Hong Jiang; Parikh, S.; Lionbarger, M.; Nedovic, N.; Yamamoto, T.)
Abstract	We present a 46Gb/s 2:1 multiplexer and a source series terminated full rate driver for high speed chip-to-chip communications. The multiplexer and the driver are implemented using the pseudo-differential static CMOS circuit. Transmitter driver uses the push-pull structure to produce a VDD peak-to-peak differential voltage swing. The circuit uses no current mode logic gates or large on-chip passive devices aside from series-connected on-chip resistor and the T-coil used to minimize the return loss. We confirmed the total jitter of about 7ps at 46Gb/s and eye opening of 0.605UI up to 50 Gb/s on the test circuit fabricated in 20nm CMOS technology. Measured power consumption is 38.7mW at 46Gb/s (0.84pJ/b power efficiency).
Starting Page	377
Ending Page	380
File Size	1237311
Page Count	4
File Format	PDF
ISBN	9781479940905
e-ISBN	9781479940899
DOI	10.1109/ASSCC.2014.7008939
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-10
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transmitters CMOS integrated circuits Multiplexing CMOS technology Jitter Loss measurement Resistors T-coil multiplexer source-series terminated driver transmitter CMOS push-pull termination
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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