NDLI: Channel BER Measurement for a 5.8Gb/s/pin unidirectional differential I/O for DRAM application

Content Provider	IEEE Xplore Digital Library
Author	Hoeju Chung Youngchan Jang Youngdon Choi Hwanwook Park Jaekwan Kim Soouk Lim Jung Sunwoo Moonsook Park Hyungwsuk Kim Sang-Yun Kim Hyun-Kyung Kim Su-Jin Chung Eun-Mi Lee Youngju Kim Yun-Sang Lee Woo-Seop Kim Jung-Bae Lee Changhyun Kim
Copyright Year	2008
Description	Author affiliation: ATD Team, Samsung Electron. Co., Ltd., Hwasung (Hoeju Chung; Youngchan Jang; Youngdon Choi; Hwanwook Park; Jaekwan Kim; Soouk Lim; Jung Sunwoo; Moonsook Park; Hyungwsuk Kim; Sang-Yun Kim; Hyun-Kyung Kim; Su-Jin Chung; Eun-Mi Lee; Youngju Kim; Yun-Sang Lee; Woo-Seop Kim; Jung-Bae Lee; Changhyun Kim)
Abstract	A 5.8 Gb/s/pin DRAM with unidirectional differential I/Os and 1 Gbit memory core was designed and 23.2 GB/s memory module was assembled. Tx BER measurement on an electrical test board similar to real memory sub-systempsilas environment was performed and the results show that no additional coding for the differential I/O protection, like CRC, seems to be required up to 5.8 Gb/s/pin operation. Also, an efficient timing usage method using matched path for a possible implementation of CRC computation in ODIC architecture was proposed.
Starting Page	29
Ending Page	32
File Size	638958
Page Count	4
File Format	PDF
ISBN	9781424426041
DOI	10.1109/ASSCC.2008.4708721
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-03
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bit error rate Random access memory Cyclic redundancy check Assembly Electric variables measurement Testing Performance evaluation Protection Timing Computer architecture
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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