NDLI: An all-digital, highly scalable architecture for measurement of spatial variation in digital circuits

Content Provider	IEEE Xplore Digital Library
Author	Drego, N. Chandrakasan, A. Boning, D.
Copyright Year	2008
Description	Author affiliation: Massachusetts Inst. of Technol., MA (Drego, N.; Chandrakasan, A.; Boning, D.)
Abstract	Increased variation in CMOS processes due to scaling results in greater reliance on accurate variation models in developing circuit methods to mitigate variation. This paper investigates specific variation parameters and their measurement approach for use in such models, leading to critical considerations in aggressive voltage scaling systems. We describe a test-chip in 90 nm CMOS containing all-digital measurement circuits capable of extracting accurate variation data. Specifically, we use replicated 64-bit Kogge-Stone adders, ring-oscillators (ROs) of varying gate type and stage length and an all-digital, sub-picosecond resolution delay measurement circuit to provide spatial variation data for digital circuits. Measurement data from the test-chips indicate that 1) relative variation is significantly larger in low-voltage domains, 2) within-die variation is spatially uncorrelated, and 3) die-to-die (or global) variation is strongly correlated, but degrades toward uncorrelated as the power-supply voltage is lowered.
Starting Page	393
Ending Page	396
File Size	228140
Page Count	4
File Format	PDF
ISBN	9781424426041
DOI	10.1109/ASSCC.2008.4708810
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-03
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital circuits Circuit testing Semiconductor device modeling Voltage CMOS process Data mining Adders Spatial resolution Delay Length measurement
Content Type	Text
Resource Type	Article

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