NDLI: A 4Gbps 3-bit parallel transmitter with the crosstalk-induced jitter compensation using TX data timing control

Content Provider	IEEE Xplore Digital Library
Author	Hae-Kang Jung Kyoungho Lee Jong-Sam Kim Jae-Jin Lee Jae-Yoon Sim Hong-June Park
Copyright Year	2008
Description	Author affiliation: Hynix Semicond. Inc., Icheon (Jong-Sam Kim; Jae-Jin Lee) \|\| Pohang Univ. of Sci. & Technol., Pohang (Kyoungho Lee; Jae-Yoon Sim; Hong-June Park)
Abstract	By using the data timing control at transmitter (TX) side, the crosstalk-induced jitter (CIJ) is compensated in a 4 Gbps single-ended transmitter with 3-bit parallel data. CIJ is induced by the propagation velocity difference between the signal modes of parallel transmission lines. This velocity difference was compensated for by sending data early or late at TX according to the signal modes, so that the signals of different modes arrive at receiver at the same time. The proposed TX was implemented by using a 0.18 mum CMOS process. The parallel transmission lines used in the measurements are 4-inch long, have the minimum-allowed spacing between transmission lines to maximize CIJ. CIJ was measured to be reduced by about 50% from 53 ps to 27 ps at 4 Gbps excluding the random jitter component of 72 ps added at the TX side. The scheme used in this work can be expanded to more than three transmission lines.
Starting Page	201
Ending Page	204
File Size	282904
Page Count	4
File Format	PDF
ISBN	9781424426041
DOI	10.1109/ASSCC.2008.4708763
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-03
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transmitters Crosstalk Timing jitter Microstrip Signal processing Transmission lines Couplings Electromagnetic propagation Semiconductor device noise Clocks
Content Type	Text
Resource Type	Article

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