NDLI: High-performance NAND flash controller exploiting parallel out-of-order command execution

Content Provider	IEEE Xplore Digital Library
Author	Yu-Hsiang Kao Juinn-Dar Huang
Copyright Year	2010
Description	Author affiliation: Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C. (Yu-Hsiang Kao; Juinn-Dar Huang)
Abstract	NAND flash memory is one of the most important components in modern non-volatile storage media. However, long command setup time and slow I/O interface frequency of current NAND flash device has been limiting the bandwidth of data transfer. In this paper, we propose a high-performance NAND flash controller architecture by exploiting two techniques - parallel out-of-order execution of multi-die commands and two-plane address translation. By these two techniques, the number of commands being executed in parallel can be maximized and the average execution time per command can thus be greatly reduced to achieve higher performance. The experimental results show that the proposed NAND flash controller can improve the data access performance in both read and program for at least 18% as compared to a baseline NAND flash controller.
Starting Page	160
Ending Page	163
File Size	218511
Page Count	4
File Format	PDF
ISBN	9781424452699
DOI	10.1109/VDAT.2010.5496715
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-26
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Out of order Frequency Logic arrays Flash memory Solid state circuits Timing Programmable logic arrays Decoding Nonvolatile memory Bandwidth
Content Type	Text
Resource Type	Article

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