NDLI: Design and implementation of a FPGA chip FDP3P7

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VLSI Design, Automation and Test(VLSI-DAT)

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Proceedings of 2010 International Symposium on VLSI Design, Automation and Test

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Table of content

The Exascale challenge

K2 the changing role of test in semiconductor manufacturing

K3 Moore's Law in the Era of GPU Computing

Thermo-mechanical stress characterization of tungsten-fill through-silicon-via

3D integration technology for energy efficient system design

Verifying thermal/thermo-mechanical behavior of a 3D stack - challenges and solutions

Via mid through silicon vias - the manufacturability outlook

ThruChip interface for 3D system integration

Real-time hierarchical bus system with Static arbitration using timer-controlled Priority Allocator for a multi-media SoC

Exploring parallelism during processor design space exploration

A configurable SystemC virtual platform for early software development and its sub-system for hardware verification

Platform-based design automation - Platform Core Compiler

Efficient LDPC decoder implementation for DVB-S2 system

Design of a digital power IC

A novel dynamic over-drive scheme for LCD with dynamic driving gamma curves

Digitally-assisted analog designs for submicron CMOS technology

A 400-MHz super-regenerative receiver with a fast digital frequency calibration

Fully integrated self-quenched super-regenerative Impulse-FM-UWB transceiver for WBAN

Design challenges for sense amplifier and wireless link in high-density neural recording implants

A wide-range all-digital delay-locked loop in 65nm CMOS technology

Energy efficient bootstrapped CMOS large RC-load driver circuit for ultra low-voltage VLSI

Low-Power FinFET design schemes for NOR address decoders

A low voltage and process variation tolerant SRAM cell in 90-nm CMOS

A 65nm CMOS dual-band RF receiver front-end for DVB-H

A wide-locking range divide-by-2 LC-tank injection-locked frequency divider

A 56µW VGA with 5MHz bandwidth and 47dB gain-range in 90nm CMOS

Design and implementation of a passive UHF RFID-based Real Time Location System

Improving testing and diagnosis efficiency for regular memory arrays

Yield-enhancement techniques for 3D random access memories

A nonlinear PRNG using digitized logistic map with self-reseeding method

ATE assisted test response compaction

Circuit techniques for wireless bioelectrical interfaces

Silicon RF NMR biomolecular sensor - review

MEMS packaging technologies & applications

Interface electronics for MEMS-based wireless sensing applications

Traffic-thermal mutual-coupling co-simulation platform for three-dimensional Network-on-Chip

Cache-aware task scheduling on multi-core architecture

Implementation of JVM tool interface on Dalvik virtual machine

Conditional threshold wear-leveling algorithm for multi-channel NAND flash memory

A fast ranking-based method for intra mode decision in H.264/AVC encoder

A variable-length FFT processor for 4×4 MIMO-OFDM systems

High-performance NAND flash controller exploiting parallel out-of-order command execution

Randomness enhancement for a Digitalized Modified-Logistic Map based Pseudo Random Number Generator

Performance-driven architectural synthesis for distributed register-file microarchitecture considering inter-island delay

An efficient hybrid LUT/SOP reconfigurable architecture

Dangling-wire avoidance routing for crossbar switch structured ASIC design style

Reachability analysis of sequential circuits

An integrating analog-to-digital data converter with variable resolution

A 10-bit piplined A/D converter with split calibration and opamp-sharing technique

A 1V 663µW 15-bit audio ΔΣ modulator in 0.18µm CMOS

A 0.6-V delta-sigma ADC with 57-dB dynamic range

Inter and intra kernel reuse analysis driven pipelining on Chip-Multiprocessors

Run-time Reconfiguration of expandable cache for embedded systems

Design of on-chip bus with OCP interface

A BU-based rate control design for H.264 and AVS video coding with ROI support

Predicting multi-core system Fmax by data-learning methodology

Diagnostic test generation for small delay defect diagnosis

A robust linear triangle wave generator for ADC testing

Self-Calibrate two-step digital setup/hold time measurement

A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression

Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

A 35.56GHz all-digital phase-locked loop with high resolution varactors

Energy-efficient, decision feedback equalization Using SAR-like capacitive charge summation

150mV sub-threshold Asynchronous multiplier for low-power sensor applications

A mixed style multiplier architecture for low dynamic and leakage power dissipation

Optimum leakage dynamic array design

Compact precharging-transistor-less dynamic circuits for high noise-immunity applications

Placement of temperature sensors under process variations

DNA Microarray placement for improved performance and reliability

A temperature-aware global router

Provably all-convex optimal minimum-error convex fitting algorithm using linear programming

A one-time implantable wireless power bidirectional transmission spinal cord stimulation system

A 0.5mW high dynamic range fast CMOS charge preamplifier

A 1-V low-noise readout front-end for biomedical applications in 0.18-µm CMOS

A 0.35-1 V 0.2-3 GS/s 4-bit low-power flash ADC for a solar-powered wireless module

Design and implementation of a FPGA chip FDP3P7

A semi-digital cascaded CDR with fast phase acquisition and adaptive resolution control

A low-area and short-time scan-based embedded delay measurement using signature registers

A high performance binary TO BCD converter for decimal multiplication

A 3–5-GHz LNA and mixer for an UWB RF front-end

Modelling stuck-at faults in combinational circuits with generalized stochastic petri nets

An 8-bit LCD source driver with push- pull low-power output buffer amplifiers

A peak-current controlled single-inductor dual-output DC-DC buck converter with a time-multiplexing scheme

LP-based multi-mode multi-corner clock skew optimization

Lump devices mapping between designer's schematic and layout extracted schematic in microwave frequency

Quadruple filtering schedule for H.264/AVC deblocking filter

Using the charge recycling technique for low power PLA design

Minimizing ECO routing for FIB

A polymer-based gas sensor array and its adaptive interface circuit

Low-complexity Reed-Solomon decoder for Blu-ray Disc applications

An efficient parallel VLSI architecture for H.264/AVC fractional motion estimation

2010 international symposium on VLSI design, automation and test organization

2009 International Symposium on VLSI Design, Automation and Test

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

2006 International Symposium on VLSI Design, Automation and Test

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).

Design and implementation of a FPGA chip FDP3P7

Content Provider	IEEE Xplore Digital Library
Author	Fang Wu Jian Wang Jinmei Lai Liyun Wang
Copyright Year	2010
Description	Author affiliation: ASIC & System State Key Lab, Fudan University, 825 Zhang Heng Road, Shanghai, China, 201203 (Fang Wu; Jian Wang; Jinmei Lai; Liyun Wang)
Abstract	A novel Fudan programmable logic device FDP3P7 has been designed and implemented with 0.18um CMOS logic 1P6M process. Besides that the novel design method used in FDP2008 are all adopted in this chip, the overall chip array is enlarged from 20×30 logic TILEs to 32×48. Four PLLs are added on the four corners of the chip to produce various in-chip clocks and decrease the clock skew. More Block RAMs, programmable IOBs and IO pads are also included to improve the user available configurable resource. The clock network is also redesigned to facilitate the larger chip scale. The total layout of FDP3P7 is 9.4mm×9.3mm, and the test results shows that the chip works correctly and efficiently.
Starting Page	304
Ending Page	306
File Size	150486
Page Count	3
File Format	PDF
ISBN	9781424452699
DOI	10.1109/VDAT.2010.5496749
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-26
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Routing Random access memory Delay Tiles Phase locked loops Integrated circuit interconnections
Content Type	Text
Resource Type	Article

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