NDLI: PMCD: a parallel multi-controller design for solid-state drives

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PMCD: a parallel multi-controller design for solid-state drives

Content Provider	ACM Digital Library
Author	Chou, Maw-Yi Wu, Chin-Hsien
Abstract	NAND ash memory has advanced along with the wave of consumer electronics and embedded systems, because of its advantages of non-volatility, lower-power consumption, faster access, and shock-resistance. Recently, SSDs (Solid-State Drives) which use NAND flash memory have replaced HDDs (Hard-Disk Drives) in many applications. However, NAND flash memory that has special characteristics (e.g., asymmetrical operations, out-of-place updates, and erase limitation) could have performance impacts on SSDs. Currently, the internal architecture of a SSD needs multiple controllers to handle and manage NAND flash chips. However, one controller is in charge of some specific NAND flash chips on its own bus and can't access other NAND flash chips that owned by other controllers. We call the situation as the bus constraint. The bus constraint will reduce the controllers' execution parallelism when multiple requests will access the chips on the same bus. To overcome the problem, we will propose a parallel multi-controller design (PMCD) in the paper. We will implement PMCD and the traditional multi-controller design (TMCD) on an FPGA-based development board (i.e., Altera DE2). According to our experimental results, PMCD can increase about 27.3% performance when compared to TMCD, and the overhead is acceptable.
Starting Page	416
Ending Page	421
Page Count	6
File Format	PDF
ISBN	9781450323482
DOI	10.1145/2513228.2513252
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-10-01
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Nand flash memory Solid-state drive (ssd) Multi controller
Content Type	Text
Resource Type	Article

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