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Content Provider | IEEE Xplore Digital Library |
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Author | Shouming Wei Qinsong Qian Weifeng Sun Jing Zhu Siyang Liu |
Copyright Year | 2011 |
Description | Author affiliation: National ASIC System Engineering Research Center, Southeast University, Nanjing, 210096, China (Shouming Wei; Qinsong Qian; Weifeng Sun; Jing Zhu; Siyang Liu) |
Abstract | The Electrostatic discharge (ESD) capabilities of the gate-ground NMOS devices in the circuits with and without input capacitance are experimentally compared in this paper. The experimental results show that the input capacitor can reduce the ESD robustness, which has been explained in detail by using two-dimensional simulator. At last, a novel design is also proposed to improve the ESD protection behavior of the CMOS integrated circuits with the input capacitor. The proposed design is validated by using two-dimensional simulations and experimental analysis. |
Starting Page | 1 |
Ending Page | 2 |
File Size | 259433 |
Page Count | 2 |
File Format | |
ISBN | 9781457719981 |
e-ISBN | 9781457719974 |
e-ISBN | 9781457719967 |
DOI | 10.1109/EDSSC.2011.6117689 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2011-11-17 |
Publisher Place | China |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Electrostatic discharges Capacitors Substrates Robustness Transistors Stress Logic gates improved structure Electro-static discharge input capacitor |
Content Type | Text |
Resource Type | Article |
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