NDLI: 28V ESD clamp in CMOS 40nm process

Content Provider	IEEE Xplore Digital Library
Author	Chowdary, G. Neri, F. Somajayula, S. Notermans, G.
Copyright Year	2012
Description	Author affiliation: Aura Semiconductors, Bangalore, India (Chowdary, G.; Somajayula, S.) \|\| Samsung Electronics, Suwon, South Korea (Neri, F.) \|\| ST-Ericsson, Schlieren, Switzerland (Notermans, G.)
Abstract	The thin gate oxide in nanoscale CMOS technologies is a serious challenge to the electrostatic discharge (ESD) robustness of ICs. This paper describes a sophisticated design solution for a 28V ESD clamp integrated in a 40nm CMOS product using only 2.75V transistors. It is suitable for I/O interface in SoC chips for mobile application and allows a battery charger to be connected directly to the chip. The presented clamp passed ESD/Latch-up test for HBM 3KV, 30V over-voltage test and 1000-hours prolonged operation life-time test.
Starting Page	1
Ending Page	2
File Size	317508
Page Count	2
File Format	PDF
ISBN	9781467356947
e-ISBN	9781467356961
DOI	10.1109/EDSSC.2012.6482885
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-03
Publisher Place	Thailand
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electrostatic discharges Clamps Logic gates CMOS integrated circuits Transistors CMOS technology System-on-chip 28V electrostatic discharge (ESD) on-chip ESD protection gate oxide over-stress Human-Body Model (HBM) 40nm CMOS
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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