NDLI: A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis

Content Provider	IEEE Xplore Digital Library
Author	Sinha, S. Dhawan, U. Siew Kei Lam Srikanthan, T.
Copyright Year	2011
Abstract	Hardware binding plays an important role in the performance of a design on FPGAs. Good timing performance requires that the hardware binding be as efficient as possible. It is often acceptable to let the area increase within a tolerance limit if the timing could be improved. In this paper, we propose a new hardware binding algorithm.. It performs simultaneous FU and register binding incorporating device-specific delay information for functional units and multiplexers. The proposed approach, implemented within a C to RTL framework has resulted in significant improvement in maximum achievable clock frequency compared to previously proposed Weighted Bipartite Matching and Compatibility Path Based algorithms. The associated increase in area is also within a very tight margin and hence quite acceptable even when there is an area constraint. Also, when compared to WBM and CPB methods, the proposed algorithm improves clock period on average by 17.6% and 9.7% respectively without any penalty in area. When compared with ECPB algorithm, clock period is improved by 5.6% on average at a small area cost of 5.5%.
Starting Page	278
Ending Page	283
File Size	233010
Page Count	6
File Format	PDF
ISBN	9781457708039
ISSN	21592477
DOI	10.1109/ISVLSI.2011.18
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-04
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Registers Algorithm design and analysis Hardware Clocks Table lookup Delay reduction High Level Synthesis FPGA
Content Type	Text
Resource Type	Article

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