NDLI: Power-safe test application using an effective gating approach considering current limits

Content Provider	IEEE Xplore Digital Library
Author	Wei Zhao Tehranipoor, M. Chakravarty, S.
Copyright Year	2011
Description	Author affiliation: ECE Department, University of Connecticut, USA (Wei Zhao; Tehranipoor, M.) \|\| LSI Corporation, USA (Chakravarty, S.)
Abstract	Freezing scan cell outputs can block transitions to the combinational components thus reduce shift power. The extra logic introduces area overhead, reduces timing margin and increases power in capture mode. This paper proposes a partial gating flow that calculates instance toggling probability to identify power sensitive cells. The toggling rate reduction tendency is demonstrated to be useful in estimating how much extra logic is needed to achieve a desired shift power reduction rate for a design. To ensure power safety across entire test session, the toggling rate metric is enhanced to consider the effect of capture power increase. A complementary pair of weights can adjust the power change in shift and capture modes, thus achieve an overall balanced power safety. The toggling probability metric along with the proposed flow provide a flexibility that benefits various practical power requirements when considering current limits of both circuit and tester.
Starting Page	160
Ending Page	165
File Size	4289556
Page Count	6
File Format	PDF
ISBN	9781612846576
ISSN	10930167
e-ISBN	9781612846569
DOI	10.1109/VTS.2011.5783777
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Safety Mathematical model Probability Benchmark testing Clocks weighted switching low power test scan cell gating shift power capture power tester probe
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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